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[Qemu-devel] [PATCH 0/2] target-arm: ESR IL bit fixes

From: Peter Maydell
Subject: [Qemu-devel] [PATCH 0/2] target-arm: ESR IL bit fixes
Date: Tue, 17 May 2016 13:14:16 +0100

These patches fix some problems with setting the IL bit in
ESR syndrome register values:
 * we were not setting IL for insn abort, watchpoint or swstep
   (which should all always have IL==1)
 * we were trying to set the IL bit in arm_cpu_do_interrupt_aarch64()
   if doing a 32->64 bit exception entry, which was wrong in
   several ways; instead we should just rely on exception.syndrome
   already having the correct IL bit value

The patches are intended to apply on top of target-arm.next:
 https://git.linaro.org/people/peter.maydell/qemu-arm.git target-arm.next
(which has Edgar's patch which gets us correct IL bit values for
data abort exceptions).

Peter Maydell (2):
  target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
  target-arm: Don't try to set ESR IL bit in

 target-arm/helper.c    | 3 ---
 target-arm/internals.h | 6 +++---
 2 files changed, 3 insertions(+), 6 deletions(-)


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