[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS6
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64 |
Date: |
Fri, 18 Sep 2015 12:25:34 +0100 |
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0883782..a59b670 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4765,12 +4765,6 @@ static inline void gen_mtc0_store32 (TCGv arg,
target_ulong off)
tcg_temp_free_i32(t0);
}
-static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
-{
- tcg_gen_ext32s_tl(arg, arg);
- tcg_gen_st_tl(arg, cpu_env, off);
-}
-
static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -5629,12 +5623,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -5884,7 +5880,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 14:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -6057,7 +6053,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -6160,7 +6156,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 30:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
--
2.1.0
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 03/10] target-mips: Fix RDHWR on CP0.Count, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 05/10] target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing QEMU to hang, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 08/10] target-mips: add missing restriction in DAUI instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64,
Leon Alrae <=
- [Qemu-devel] [PULL 10/10] target-mips: improve exception handling, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random index of TLBWR instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 01/10] target-mips: Use tcg_gen_extrh_i64_i32, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 04/10] target-mips: get rid of MIPS_DEBUG, Leon Alrae, 2015/09/18
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2015/09/18