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[Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random index of TLBWR instruction |
Date: |
Fri, 18 Sep 2015 12:25:31 +0100 |
From: Serge Vakulenko <address@hidden>
The LFSR algorithm, used for generating random TLB indexes for TLBWR
instruction, was inclined to produce a degenerate sequence in some cases.
For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2...
When replaced with LCG algorithm from ISO/IEC 9899 standard, the sequence
looks much better, with about the same computational effort needed.
Signed-off-by: Serge Vakulenko <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
hw/mips/cputimer.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
index 577c9ae..1603600 100644
--- a/hw/mips/cputimer.c
+++ b/hw/mips/cputimer.c
@@ -30,13 +30,16 @@
/* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUMIPSState *env)
{
- static uint32_t lfsr = 1;
+ static uint32_t seed = 1;
static uint32_t prev_idx = 0;
uint32_t idx;
/* Don't return same value twice, so get another value */
do {
- lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
- idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+ /* Use a simple algorithm of Linear Congruential Generator
+ * from ISO/IEC 9899 standard. */
+ seed = 1103515245 * seed + 12345;
+ idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) +
+ env->CP0_Wired;
} while (idx == prev_idx);
prev_idx = idx;
return idx;
--
2.1.0
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 03/10] target-mips: Fix RDHWR on CP0.Count, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 05/10] target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing QEMU to hang, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 08/10] target-mips: add missing restriction in DAUI instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 10/10] target-mips: improve exception handling, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random index of TLBWR instruction,
Leon Alrae <=
- [Qemu-devel] [PULL 01/10] target-mips: Use tcg_gen_extrh_i64_i32, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 04/10] target-mips: get rid of MIPS_DEBUG, Leon Alrae, 2015/09/18
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2015/09/18