Re: [Qemu-devel] [PATCH v1 03/10] target-arm: Add AArch64 access to PAR_EL1

[Alistair Francis]

On Thu, Sep 3, 2015 at 1:14 PM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Thanks,

Alistair

> ---
>  target-arm/helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 4234e7c..a057a70 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2993,6 +2993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
>        .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
> +    { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS,
> +      .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
> +      .access = PL1_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
> +      .writefn = par_write },
>  #endif
>      /* TLB invalidate last level of translation table walk */
>      { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 
> 5,
> --
> 1.9.1
>
>