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Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

From: Pavel Fedin
Subject: Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class
Date: Sun, 26 Jul 2015 17:03:14 +0300


> > +
> > +typedef struct gicv3_irq_state {
> > +    /* The enable bits are only banked for per-cpu interrupts.  */
> > +    uint64_t enabled;
> > +    uint64_t pending;
> > +    uint64_t active;
> > +    uint64_t level;
> > +    uint64_t group;
> Why are these uint64_t ?

 I studied the code for a little bit more. These are bitmasks, where bit 
represents a CPU. Take a look at gicv3_internal.h, GIC_SET/CLEAR/TEST_xxx 
macros. 'cm' stands for 'cpu mask'.
 This is currently not used by my code, this is mainly for Shlomo's SW 
emulation. However, there is some usage in common class initialization code.

 And i will fix up all badly understood comments.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

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