Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode.

[Aurelien Jarno]

On 2015-07-05 20:05, Serge Vakulenko wrote:
> >>      } else {
> >>          /* A MIPS configured with compatibility or VInt (Vectored 
> >> Interrupts)
> >> diff --git a/target-mips/helper.c b/target-mips/helper.c
> >> index 8e3204a..7e25998 100644
> >> --- a/target-mips/helper.c
> >> +++ b/target-mips/helper.c
> >> @@ -574,23 +574,31 @@ void mips_cpu_do_interrupt(CPUState *cs)
> >>              unsigned int vector;
> >>              unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
> >>
> >> -            pending &= env->CP0_Status >> 8;
> >>              /* Compute the Vector Spacing.  */
> >>              spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
> >>              spacing <<= 5;
> >>
> >> -            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
> >> +            if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> >> +                /* For VEIC mode, the external interrupt controller feeds 
> >> the
> >> +                 * vector through the CP0Cause IP lines. */
> >> +                vector = pending;
> >> +
> >> +                /* Architecturally, this is chip-specific behavior.
> >> +                 * TODO: some processors, like PIC32MZ,
> >> +                 * provide vector in a different way.
> >> +                 * Some processors, like PIC32, have a separate
> >> +                 * bit INTCON.MVEC to explicitly enable vectored mode,
> >> +                 * disabled by default. */
> >> +                spacing = 0;
> >> +            } else {
> >>                  /* For VInt mode, the MIPS computes the vector 
> >> internally.  */
> >> +                pending &= env->CP0_Status >> 8;
> >>                  for (vector = 7; vector > 0; vector--) {
> >>                      if (pending & (1 << vector)) {
> >>                          /* Found it.  */
> >>                          break;
> >>                      }
> >>                  }
> >> -            } else {
> >> -                /* For VEIC mode, the external interrupt controller feeds 
> >> the
> >> -                   vector through the CP0Cause IP lines.  */
> >> -                vector = pending;
> >>              }
> >
> > The changes looks correct, but I do wonder why you swap the test on
> > CP0_Config3. It would be less changes to just move the pending masking
> > with CP0_Status inside the VInt mode.
> 
> According to MIPS PRA spec (MD00090), VInt bit becomes do-not-care
> when Config3.VEIC is enabled. So it makes little sense to rely on it's
> value here. And it makes it easier to understand this way. EIC and
> VInt modes are quite different: better not to mix them up.

Ok I understand now.

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net