[Qemu-devel] [PATCH 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <address@hidden>
---
 target-tricore/translate.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 663b2a0..1c37e48 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3485,7 +3485,7 @@ static void gen_compute_branch(DisasContext *ctx, 
uint32_t opc, int r1,
  * Functions for decoding instructions
  */
 
-static void decode_src_opc(DisasContext *ctx, int op1)
+static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
 {
     int r1;
     int32_t const4;
@@ -3546,6 +3546,12 @@ static void decode_src_opc(DisasContext *ctx, int op1)
         const4 = MASK_OP_SRC_CONST4(ctx->opcode);
         tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
         break;
+    case OPC1_16_SRC_MOV_E:
+        if (tricore_feature(env, TRICORE_FEATURE_16)) {
+            tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
+            tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
+        } /* TODO: else raise illegal opcode trap */
+        break;
     case OPC1_16_SRC_SH:
         gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
         break;
@@ -3883,9 +3889,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, 
DisasContext *ctx)
     case OPC1_16_SRC_LT:
     case OPC1_16_SRC_MOV:
     case OPC1_16_SRC_MOV_A:
+    case OPC1_16_SRC_MOV_E:
     case OPC1_16_SRC_SH:
     case OPC1_16_SRC_SHA:
-        decode_src_opc(ctx, op1);
+        decode_src_opc(env, ctx, op1);
         break;
 /* SRR-format */
     case OPC1_16_SRR_ADD:
-- 
2.4.0