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Re: [Qemu-devel] [PATCH v3 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v3 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked |
Date: |
Mon, 27 Apr 2015 16:00:41 +0100 |
On 15 April 2015 at 17:02, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
> Extensions or in GICv2 in independent from Security Extensions.
> This makes it possible to enable forwarding of interrupts from
> the CPU interfaces to the connected processors for Group0 and Group1.
>
> We also allow to set additional bits like AckCtl and FIQEn by changing
> the type from bool to uint32. Since the field does not only store the
> enable bit anymore and since we are touching the vmstate, we use the
> opportunity to rename the field to cpu_control.
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
>
> ---
>
> v1 -> v2
> - Rework gic_set_cpu_control() and gic_get_cpu_control() to close gap on
> handling GICv1 wihtout security extensions.
> - Fix use of incorrect control index in update.
> ---
> hw/intc/arm_gic.c | 82
> +++++++++++++++++++++++++++++++++++++---
> hw/intc/arm_gic_common.c | 5 ++-
> hw/intc/arm_gic_kvm.c | 8 ++--
> hw/intc/armv7m_nvic.c | 2 +-
> hw/intc/gic_internal.h | 14 +++++++
> include/hw/intc/arm_gic_common.h | 2 +-
> 6 files changed, 100 insertions(+), 13 deletions(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index b9dfde3..b402e00 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -66,7 +66,7 @@ void gic_update(GICState *s)
> for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
> cm = 1 << cpu;
> s->current_pending[cpu] = 1023;
> - if (!s->enabled || !s->cpu_enabled[cpu]) {
> + if (!s->enabled || !(s->cpu_control[cpu][1] & 1)) {
This breaks no-security-extensions configs at this point
in the patchseries, because here we always test
cpu_control[cpu][1] bit 0...
> +void gic_set_cpu_control(GICState *s, int cpu, uint32_t value)
> +{
> + if (!s->security_extn) {
> + if (s->revision == 1) {
> + s->cpu_control[cpu][1] = value & 0x1;
> + DPRINTF("CPU Interface %d %sabled\n", cpu,
> + s->cpu_control[cpu][1] ? "En" : "Dis");
> + } else {
> + /* Write to Secure instance of the register */
> + s->cpu_control[cpu][0] = value & GICC_CTLR_S_MASK;
> + /* Synchronize EnableGrp1 alias of Non-secure copy */
> + s->cpu_control[cpu][1] &= ~GICC_CTLR_NS_EN_GRP1;
> + s->cpu_control[cpu][1] |=
> + (value & GICC_CTLR_S_EN_GRP1) ? GICC_CTLR_NS_EN_GRP1 : 0;
...but here we only set bit 0 of [cpu][1] if bit 1 of the value is
set. So a guest which only sets bit 0 stops working (my testcase
is an aarch64 linux guest on the virt board).
This does seem to start working again later in the series, so
clearly something needs to be rearranged so we don't break
bisection.
-- PMM
- [Qemu-devel] [PATCH v3 13/16] hw/intc/arm_gic: Change behavior of IAR writes, (continued)
- [Qemu-devel] [PATCH v3 13/16] hw/intc/arm_gic: Change behavior of IAR writes, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 04/16] hw/intc/arm_gic: Add Security Extensions property, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 06/16] hw/intc/arm_gic: Add Interrupt Group Registers, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 01/16] hw/intc/arm_gic: Request FIQ sources, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Greg Bellows, 2015/04/15
- Re: [Qemu-devel] [PATCH v3 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 05/16] hw/intc/arm_gic: Add ns_access() function, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 14/16] hw/intc/arm_gic: Restrict priority view, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 15/16] hw/intc/arm_gic: Break out gic_update() function, Greg Bellows, 2015/04/15
- [Qemu-devel] [PATCH v3 16/16] hw/intc/arm_gic: add gic_update() for grouping, Greg Bellows, 2015/04/15