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[Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register defini
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition |
Date: |
Thu, 5 Feb 2015 14:02:45 +0000 |
From: Greg Bellows <address@hidden>
Added CP register definitions for SP_EL1 and SP_EL2.
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 29f3b62..79c54a9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .accessfn = sp_el0_access,
.type = ARM_CP_NO_MIGRATE,
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
+ { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_NO_MIGRATE,
+ .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_MIGRATE,
@@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.access = PL2_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
.resetvalue = 0 },
+ { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_NO_MIGRATE,
+ .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr(), (continued)
- [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 23/28] target-arm: Fix brace style in reindented code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 12/28] hw/arm/virt: explain device-to-transport mapping in create_virtio_devices(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition,
Peter Maydell <=
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init, Peter Maydell, 2015/02/05