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[Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7 |
Date: |
Thu, 5 Feb 2015 14:02:52 +0000 |
Support guest CPUs which need 7 MMU index values.
Add a comment about what would be required to raise the limit
further (trivial for 8, TCG backend rework for 9 or more).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
include/exec/cpu_ldst.h | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 0e825ea..1673287 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -244,9 +244,31 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong
addr, int mmu_idx);
#undef MEMSUFFIX
#endif /* (NB_MMU_MODES >= 6) */
-#if (NB_MMU_MODES > 6)
-#error "NB_MMU_MODES > 6 is not supported for now"
-#endif /* (NB_MMU_MODES > 6) */
+#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
+
+#define CPU_MMU_INDEX 6
+#define MEMSUFFIX MMU_MODE6_SUFFIX
+#define DATA_SIZE 1
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 2
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 4
+#include "exec/cpu_ldst_template.h"
+
+#define DATA_SIZE 8
+#include "exec/cpu_ldst_template.h"
+#undef CPU_MMU_INDEX
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 7) */
+
+#if (NB_MMU_MODES > 7)
+/* Note that supporting NB_MMU_MODES == 9 would require
+ * changes to at least the ARM TCG backend.
+ */
+#error "NB_MMU_MODES > 7 is not supported for now"
+#endif /* (NB_MMU_MODES > 7) */
/* these access are slower, they must be as rare as possible */
#define CPU_MMU_INDEX (cpu_mmu_index(env))
--
1.9.1
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, (continued)
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7,
Peter Maydell <=
- [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 24/28] disas/libvixl: Update to upstream VIXL 1.7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 07/28] target-arm: Split NO_MIGRATE into ALIAS and NO_RAW, Peter Maydell, 2015/02/05
- Re: [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2015/02/05