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[Qemu-devel] [PATCH] target-mips: Make CP0.Status.CU1 read-only for the
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From: |
Maciej W. Rozycki |
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Subject: |
[Qemu-devel] [PATCH] target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors |
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Date: |
Sat, 20 Dec 2014 23:00:25 +0000 |
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User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
Signed-off-by: Maciej W. Rozycki <address@hidden>
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Hi,
As we discussed previously, please apply.
[This got stuck in postponed e-mail, I thought I had sent it already.]
Maciej
qemu-mips-5kc-cu1.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c 2014-11-20
10:47:31.578938672 +0000
+++ qemu-git-trunk/target-mips/translate_init.c 2014-11-20 10:47:39.078939989
+0000
@@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] =
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0x32F8FFFF,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64,
@@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] =
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0x32F8FFFF,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64R2,
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