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[Qemu-devel] [PULL 26/30] target-mips: Fix DisasContext's ulri member in
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 26/30] target-mips: Fix DisasContext's ulri member initialization |
Date: |
Tue, 16 Dec 2014 19:49:12 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Set DisasContext's ulri member to 0 or 1 as with other bool members.
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 571b7d7..f65ed84 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19116,7 +19116,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
- ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
+ ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;
--
2.1.0
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, (continued)
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 12/30] target-mips: Restore the order of helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 16/30] target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 21/30] target-mips: gdbstub: Clean up FPU register handling, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 22/30] target-mips: Also apply the CP0.Status mask to MTTC0, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 18/30] target-mips: Fix CP0.Config3.ISAOnExc write accesses, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 19/30] target-mips: Tighten ISA level checks, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 23/30] linux-user: Use the 5KEf processor for 64-bit emulation, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 24/30] target-mips: Add missing calls to synchronise SoftFloat status, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 20/30] target-mips: Correct 32-bit address space wrapping, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 26/30] target-mips: Fix DisasContext's ulri member initialization,
Leon Alrae <=
- [Qemu-devel] [PULL 25/30] target-mips: Use local float status pointer across MSA macros, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 27/30] target-mips: convert single case switch into if statement, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 28/30] disas/mips: remove unused mips_msa_control_names_numeric[32], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 30/30] target-mips: remove excp_names[] from linux-user as it is unused, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 29/30] disas/mips: disable unused mips16_to_32_reg_map[], Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 05/30] target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 07/30] target-mips: Fix formatting in `decode_extended_mips16_opc', Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 06/30] target-mips: Enable vectored interrupt support for the 74Kf CPU, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 04/30] target-mips: Make CP0.Config4 and CP0.Config5 registers signed, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 08/30] target-mips: Fix formatting in `mips_defs', Leon Alrae, 2014/12/16