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[Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions |
Date: |
Wed, 15 Oct 2014 10:54:11 +0100 |
From: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
---
disas/mips.c | 2 ++
target-mips/translate.c | 18 ++++++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 5ebb5fd..7297825 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -1313,6 +1313,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0,
I32R6},
{"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0,
I32R6},
{"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0,
I32R6},
+{"nal", "p", 0x04100000, 0xffff0000, WR_31, 0,
I32R6},
+{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0,
I32R6},
{"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0,
I32R6},
{"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0,
I32R6},
{"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0,
I32R6},
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8088781..57c2d41 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#endif
+ case OPC_JR:
+ gen_compute_branch(ctx, op1, 4, rs, rd, sa);
+ break;
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
@@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
case OPC_XOR:
gen_logic(ctx, op1, rd, rs, rt);
break;
- case OPC_JR ... OPC_JALR:
+ case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa);
break;
case OPC_TGE ... OPC_TEQ: /* Traps */
@@ -16903,9 +16906,20 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_BLTZ:
case OPC_BGEZ:
+ gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
+ break;
case OPC_BLTZAL:
case OPC_BGEZAL:
- gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (rs == 0) {
+ /* OPC_NAL, OPC_BAL */
+ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2);
+ } else {
+ generate_exception(ctx, EXCP_RI);
+ }
+ } else {
+ gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
+ }
break;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
--
2.1.0
- [Qemu-devel] [PULL 07/28] target-mips: signal RI Exception on DSP and Loongson instructions, (continued)
- [Qemu-devel] [PULL 07/28] target-mips: signal RI Exception on DSP and Loongson instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit address wrapping, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 08/28] target-mips: move PREF, CACHE, LLD and SCD instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 09/28] target-mips: redefine Integer Multiply and Divide instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 10/28] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 12/28] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 15/28] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 18/28] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 17/28] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions,
Leon Alrae <=
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions, Leon Alrae, 2014/10/15