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[Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards aro
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions |
Date: |
Wed, 15 Oct 2014 10:54:19 +0100 |
From: Peter Maydell <address@hidden>
Add ifdef TARGET_MIPS64 guards around various functions that are only
called from helpers for TARGET_MIPS64 CPUs; this avoids compiler
warnings when building other configs.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/dsp_helper.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 2ea94a7..349f2a0 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -274,6 +274,7 @@ static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc,
int32_t a,
return result;
}
+#ifdef TARGET_MIPS64
/* a[0] is LO, a[1] is HI. */
static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
int32_t ac,
@@ -327,6 +328,7 @@ static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
set_DSPControl_overflow_flag(1, 16 + ac, env);
}
}
+#endif
static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
CPUMIPSState *env)
@@ -348,10 +350,12 @@ static inline int32_t mipsdsp_mul_u16_u16(int32_t a,
int32_t b)
return a * b;
}
+#ifdef TARGET_MIPS64
static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
{
return a * b;
}
+#endif
static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
CPUMIPSState *env)
@@ -408,10 +412,12 @@ static inline int16_t mipsdsp_rashift16(int16_t a,
target_ulong mov)
return a >> mov;
}
+#ifdef TARGET_MIPS64
static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
{
return a >> mov;
}
+#endif
static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
{
@@ -470,6 +476,7 @@ static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a,
uint8_t b)
return (temp >> 1) & 0x00FF;
}
+#ifdef TARGET_MIPS64
static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
{
uint16_t temp;
@@ -487,6 +494,7 @@ static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a,
uint8_t b)
return (temp >> 1) & 0x00FF;
}
+#endif
/* 128 bits long. p[0] is LO, p[1] is HI. */
static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
@@ -502,6 +510,7 @@ static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
p[1] = (acc >> 63) & 0x01;
}
+#ifdef TARGET_MIPS64
/* 128 bits long. p[0] is LO, p[1] is HI */
static inline void mipsdsp_rashift_acc(uint64_t *p,
uint32_t ac,
@@ -549,6 +558,7 @@ static inline void mipsdsp_rndrashift_acc(uint64_t *p,
}
}
}
+#endif
static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
CPUMIPSState *env)
@@ -599,10 +609,12 @@ static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a,
uint16_t b,
return tempI & 0x0000FFFF;
}
+#ifdef TARGET_MIPS64
static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
{
return (uint64_t)a * (uint64_t)b;
}
+#endif
static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
CPUMIPSState *env)
@@ -708,7 +720,7 @@ static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t
s,
return a << s;
}
-
+#ifdef TARGET_MIPS64
static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
CPUMIPSState *env)
{
@@ -725,6 +737,7 @@ static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t
s,
return a << s;
}
}
+#endif
static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
CPUMIPSState *env)
@@ -964,6 +977,7 @@ static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t
b, CPUMIPSState *env)
return temp & 0x00FF;
}
+#ifdef TARGET_MIPS64
static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
{
int32_t temp;
@@ -988,6 +1002,7 @@ static inline int32_t mipsdsp_add_i32(int32_t a, int32_t
b, CPUMIPSState *env)
return temp;
}
+#endif
static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
{
--
2.1.0
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, (continued)
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions,
Leon Alrae <=
- [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX, Leon Alrae, 2014/10/15
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/16
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/22