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[Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked |
Date: |
Fri, 10 Oct 2014 11:03:39 -0500 |
From: Fabian Aggeler <address@hidden>
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
-----------------
v3 -> v4
- Revert to array-based notation of far_el in combination with v7 naming
---
target-arm/cpu.c | 2 +-
target-arm/cpu.h | 19 ++++++++++++++++++-
target-arm/helper.c | 20 +++++++++++---------
3 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index e192d84..8ba72ed 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -513,7 +513,7 @@ static void arm1026_initfn(Object *obj)
ARMCPRegInfo ifar = {
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
.resetvalue = 0
};
define_one_arm_cp_reg(cpu, &ifar);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 66206f9..3240777 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -270,7 +270,24 @@ typedef struct CPUARMState {
uint64_t esr_el[4];
};
uint32_t c6_region[8]; /* MPU base/size registers. */
- uint64_t far_el[4]; /* Fault address registers. */
+ union { /* Fault address registers. */
+ struct {
+ uint64_t _unused_far0;
+#ifdef HOST_WORDS_BIGENDIAN
+ uint32_t ifar_ns;
+ uint32_t dfar_ns;
+ uint32_t ifar_s;
+ uint32_t dfar_s;
+#else
+ uint32_t dfar_ns;
+ uint32_t ifar_ns;
+ uint32_t dfar_s;
+ uint32_t ifar_s;
+#endif
+ uint64_t _unused_far3;;
+ };
+ uint64_t far_el[4];
+ };
uint64_t par_el1; /* Translation result. */
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9fdbbbf..9f0fb93 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -567,7 +567,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
.access = PL0_W, .type = ARM_CP_NOP },
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
+ offsetof(CPUARMState, cp15.ifar_ns) },
.resetvalue = 0, },
/* Watchpoint Fault Address Register : should actually only be present
* for 1136, 1176, 11MPCore.
@@ -1694,11 +1695,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s),
offsetoflow32(CPUARMState, cp15.ttbcr_ns) } },
- /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
- { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
+ { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
+ offsetof(CPUARMState, cp15.dfar_ns) } },
+ { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
- .resetvalue = 0, },
+ .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]) },
REGINFO_SENTINEL
};
@@ -4357,8 +4361,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Fall through to prefetch abort. */
case EXCP_PREFETCH_ABORT:
A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
- env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
- env->exception.vaddress);
+ A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
env->exception.fsr, (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
@@ -4368,8 +4371,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_DATA_ABORT:
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
- env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
- env->exception.vaddress);
+ A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
env->exception.fsr,
(uint32_t)env->exception.vaddress);
--
1.8.3.2
- [Qemu-devel] [PATCH v6 17/32] target-arm: add NSACR register, (continued)
- [Qemu-devel] [PATCH v6 17/32] target-arm: add NSACR register, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 19/32] target-arm: add MVBAR support, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 21/32] target-arm: make CSSELR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 23/32] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 24/32] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 25/32] target-arm: make DACR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 26/32] target-arm: make IFSR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 27/32] target-arm: make DFSR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v6 29/32] target-arm: make PAR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 31/32] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/10/10