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[Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs wi
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions |
Date: |
Fri, 10 Oct 2014 11:03:43 -0500 |
From: Fabian Aggeler <address@hidden>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8ba72ed..fa12602 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -601,6 +601,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -687,6 +688,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -754,6 +756,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -821,6 +824,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
- [Qemu-devel] [PATCH v6 24/32] target-arm: make c2_mask and c2_base_mask banked, (continued)
- [Qemu-devel] [PATCH v6 24/32] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 25/32] target-arm: make DACR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 26/32] target-arm: make IFSR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 27/32] target-arm: make DFSR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 29/32] target-arm: make PAR banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 31/32] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/10
- [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions,
Greg Bellows <=