[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions |
Date: |
Mon, 4 Aug 2014 14:53:28 +0100 |
From: Alex Bennée <address@hidden>
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 35c11e7..f630d96 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1801,12 +1801,17 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
return CP_ACCESS_OK;
}
+/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance
instructions
+ * Page D4-1736 (DDI0487A.b)
+ */
+
static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by VA (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
- uint64_t pageaddr = value << 12;
+ uint64_t pageaddr = sextract64(value << 12, 0, 56);
+
tlb_flush_page(CPU(cpu), pageaddr);
}
@@ -1815,7 +1820,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
/* Invalidate by VA, all ASIDs (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
- uint64_t pageaddr = value << 12;
+ uint64_t pageaddr = sextract64(value << 12, 0, 56);
+
tlb_flush_page(CPU(cpu), pageaddr);
}
--
1.9.1
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 11/12] target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions,
Peter Maydell <=
- [Qemu-devel] [PULL 10/12] target-arm: Fix bit test in sp_el0_access, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 02/12] hw/arm/virt: formatting: memory map, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 03/12] sd: sdhci: Fix ADMA dma_memory_read access, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 06/12] target-arm: A64: Respect SPSEL when taking exceptions, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 09/12] target-arm: Add FAR_EL2 and 3, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 01/12] hw/arm/boot: Set PC correctly when loading AArch64 ELF files, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 07/12] target-arm: Make far_el1 an array, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 05/12] target-arm: A64: Respect SPSEL in ERET SP restore, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 04/12] target-arm: A64: Break out aarch64_save/restore_sp, Peter Maydell, 2014/08/04