Re: [Qemu-devel] [PATCH v2 4/8] target-i386: preserve FPU and MSR state on INIT

[Andreas Färber]

Am 02.05.2014 16:33, schrieb Paolo Bonzini:
> Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not
> be zeroed on INIT (Table 9-1 in the Intel SDM).  Copy them out of
> CPUX86State and back in, instead of special casing env->pat.
> 
> The relevant fields are already consecutive except PAT and SMBASE.
> However:
> 
> - KVM and Hyper-V MSRs should be reset because they include memory
> locations written by the hypervisor.  These MSRs are moved together
> at the end of the preserved area.
> 
> - SVM state can be moved out of the way since it is written by VMRUN.
> 
> Cc: Andreas Färber <address@hidden>
> Signed-off-by: Paolo Bonzini <address@hidden>
> ---
>  target-i386/cpu.c    |  3 +--
>  target-i386/cpu.h    | 42 ++++++++++++++++++++++++++----------------
>  target-i386/helper.c | 10 ++++++++--
>  3 files changed, 35 insertions(+), 20 deletions(-)

Fine with me. You might as well use a third marker for zeroed-on-reset
to avoid the pat -> cpuid_level change.

If we want to widen this pattern, a macro might make sense.

Regards,
Andreas

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