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[Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K bou
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K boundaries |
Date: |
Thu, 1 May 2014 15:55:06 +0100 |
For an AArch64 CPU which supports 64K pages, having the GIC
register banks at 4K offsets is potentially awkward. Move
them out to being at 64K offsets. (This is harmless for
AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is simpler
to use the same offsets everywhere than to try to use 64K offsets
only for AArch64 host CPUs.)
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/arm/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ecff256..9c4d337 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -96,10 +96,10 @@ typedef struct VirtBoardInfo {
static const MemMapEntry a15memmap[] = {
/* Space up to 0x8000000 is reserved for a boot ROM */
[VIRT_FLASH] = { 0, 0x8000000 },
- [VIRT_CPUPERIPHS] = { 0x8000000, 0x8000 },
+ [VIRT_CPUPERIPHS] = { 0x8000000, 0x20000 },
/* GIC distributor and CPU interfaces sit inside the CPU peripheral space
*/
- [VIRT_GIC_DIST] = { 0x8001000, 0x1000 },
- [VIRT_GIC_CPU] = { 0x8002000, 0x1000 },
+ [VIRT_GIC_DIST] = { 0x8000000, 0x10000 },
+ [VIRT_GIC_CPU] = { 0x8010000, 0x10000 },
[VIRT_UART] = { 0x9000000, 0x1000 },
[VIRT_MMIO] = { 0xa000000, 0x200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
--
1.9.2
- [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 08/10] hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 07/10] target-arm: Correct a comment refering to EL0, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K boundaries,
Peter Maydell <=
- [Qemu-devel] [PULL 01/10] target-arm: Implement XScale cache lockdown operations as NOPs, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 06/10] target-arm: A64: Fix a typo when declaring TLBI ops, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 03/10] target-arm: implement WFE/YIELD as a yield for AArch64, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 04/10] target-arm: Make vbar_write 64bit friendly on 32bit hosts, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 10/10] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/05/01
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/02
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Richard W.M. Jones, 2014/05/04