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[Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr |
Date: |
Thu, 1 May 2014 15:55:02 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
For linked branches, updates to the link register happen
conceptually after the read of the branch target register.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Cc: address@hidden
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e31e069..b62db4d 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1509,8 +1509,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
switch (opc) {
case 0: /* BR */
case 2: /* RET */
+ tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
break;
case 1: /* BLR */
+ tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
break;
case 4: /* ERET */
@@ -1529,7 +1531,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
return;
}
- tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
s->is_jmp = DISAS_JUMP;
}
--
1.9.2
- [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 08/10] hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 07/10] target-arm: Correct a comment refering to EL0, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr,
Peter Maydell <=
- [Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K boundaries, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 01/10] target-arm: Implement XScale cache lockdown operations as NOPs, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 06/10] target-arm: A64: Fix a typo when declaring TLBI ops, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 03/10] target-arm: implement WFE/YIELD as a yield for AArch64, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 04/10] target-arm: Make vbar_write 64bit friendly on 32bit hosts, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 10/10] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/05/01
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/02
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Richard W.M. Jones, 2014/05/04