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[Qemu-devel] [PATCH 05/40] target-alpha: Convert opcode 0x11 to source/s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/40] target-alpha: Convert opcode 0x11 to source/sink |
Date: |
Thu, 17 Apr 2014 12:32:40 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/translate.c | 126 ++++++++++++++---------------------------------
1 file changed, 37 insertions(+), 89 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 93bdc64..b378e90 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2100,32 +2100,43 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x11:
- switch (fn7) {
- case 0x00:
- /* AND */
- if (likely(rc != 31)) {
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
+ if (fn7 == 0x20) {
+ if (rc == 31) {
+ /* Special case BIS as NOP. */
+ break;
+ }
+ if (ra == 31) {
+ /* Special case BIS as MOV. */
+ vc = dest_gpr(ctx, rc);
+ if (islit) {
+ tcg_gen_movi_i64(vc, lit);
} else {
- tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
+ tcg_gen_mov_i64(vc, load_gpr(ctx, rb));
}
+ break;
}
+ }
+
+ vc = dest_gpr(ctx, rc);
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+
+ if (fn7 == 0x28 && ra == 31) {
+ /* Special case ORNOT as NOT. */
+ tcg_gen_not_i64(vc, vb);
+ break;
+ }
+
+ va = load_gpr(ctx, ra);
+ switch (fn7) {
+ case 0x00:
+ /* AND */
+ tcg_gen_and_i64(vc, va, vb);
break;
case 0x08:
/* BIC */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
- } else {
- tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- } else
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- }
+ tcg_gen_andc_i64(vc, va, vb);
break;
case 0x14:
/* CMOVLBS */
@@ -2137,21 +2148,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
break;
case 0x20:
/* BIS */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- } else {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], lit);
- } else {
- tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
- }
+ tcg_gen_or_i64(vc, va, vb);
break;
case 0x24:
/* CMOVEQ */
@@ -2163,39 +2160,11 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
break;
case 0x28:
/* ORNOT */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
- } else {
- tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- } else {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ~lit);
- } else {
- tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
- }
+ tcg_gen_orc_i64(vc, va, vb);
break;
case 0x40:
/* XOR */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- } else {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], lit);
- } else {
- tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
- }
+ tcg_gen_xor_i64(vc, va, vb);
break;
case 0x44:
/* CMOVLT */
@@ -2207,33 +2176,14 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
break;
case 0x48:
/* EQV */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
- } else {
- tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- } else {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ~lit);
- } else {
- tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
- }
+ tcg_gen_eqv_i64(vc, va, vb);
break;
case 0x61:
/* AMASK */
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
+ {
uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT;
-
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], lit & ~amask);
- } else {
- tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rb], ~amask);
- }
+ tcg_gen_andi_i64(vc, vb, ~amask);
}
break;
case 0x64:
@@ -2247,9 +2197,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
case 0x6C:
/* IMPLVER */
REQUIRE_REG_31(ra);
- if (rc != 31) {
- tcg_gen_movi_i64(cpu_ir[rc], ctx->implver);
- }
+ tcg_gen_movi_i64(vc, ctx->implver);
break;
default:
goto invalid_opc;
--
1.9.0
- [Qemu-devel] [PATCH 00/40] target-alpha queue, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 03/40] target-alpha: Introduce REQUIRE_REG_31, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 05/40] target-alpha: Convert opcode 0x11 to source/sink,
Richard Henderson <=
- [Qemu-devel] [PATCH 04/40] target-alpha: Introduce functions for source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 06/40] target-alpha: Convert opcode 0x12 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 02/40] target-alpha: Introduce REQUIRE_TB_FLAG, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 07/40] target-alpha: Convert opcode 0x13 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 09/40] target-alpha: Convert opcode 0x17 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 08/40] target-alpha: Convert opcode 0x14 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 01/40] target-alpha: fix the braces, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 11/40] target-alpha: Convert opcode 0x1A to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 13/40] target-alpha: Convert opcode 0x1C to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 10/40] target-alpha: Convert opcode 0x18 to source/sink, Richard Henderson, 2014/04/17