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Re: [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AA
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc |
Date: |
Mon, 14 Apr 2014 16:36:15 +1000 |
On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell <address@hidden> wrote:
> The AArch64 implementation of the set_pc method needs to be updated to
> handle the possibility that the CPU is in AArch32 mode; otherwise there
> are weird crashes when doing interprocessing in system emulation mode
> when an interrupt occurs and we fail to resynchronize the 32-bit PC
> with the TB we need to execute next.
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/cpu64.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 9a0c431..c673ac2 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -172,11 +172,15 @@ static void aarch64_cpu_finalizefn(Object *obj)
> static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> - /*
> - * TODO: this will need updating for system emulation,
> - * when the core may be in AArch32 mode.
> + /* It's OK to look at env for the current mode here, because it's
> + * never possible for an AArch64 TB to chain to an AArch32 TB.
> + * (Otherwise we would need to use synchronize_from_tb instead.)
> */
> - cpu->env.pc = value;
> + if (is_a64(&cpu->env)) {
> + cpu->env.pc = value;
> + } else {
> + cpu->env.regs[15] = value;
> + }
> }
>
> static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
> --
> 1.9.1
>
>
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, (continued)
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/10
- Re: [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v6 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 25/37] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 15/37] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/10