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Re: [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers |
Date: |
Mon, 14 Apr 2014 16:30:45 +1000 |
On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell <address@hidden> wrote:
> Implement the auxiliary fault status registers AFSR0_EL1 and
> AFSR1_EL1. These are present on v7 and later, and have IMPDEF
> behaviour; we choose to RAZ/WI for all cores.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
FWIW, I think .type = ARM_CP_UNIMP might be worthwhile.
> ---
> target-arm/helper.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1d1e7b4..988a8e9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -784,6 +784,15 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> + /* Auxiliary fault status registers: these also are IMPDEF, and we
> + * choose to RAZ/WI for all cores.
> + */
> + { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
> + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> + { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
> + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> /* MAIR can just read-as-written because we don't implement caches
> * and so don't need to care about memory attributes.
> */
> --
> 1.9.1
>
>
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, (continued)
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/10
- Re: [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 25/37] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/10