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[Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch3
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc |
Date: |
Fri, 28 Mar 2014 16:10:23 +0000 |
The AArch64 implementation of the set_pc method needs to be updated to
handle the possibility that the CPU is in AArch32 mode; otherwise there
are weird crashes when doing interprocessing in system emulation mode
when an interrupt occurs and we fail to resynchronize the 32-bit PC
with the TB we need to execute next.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
target-arm/cpu64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 9a0c431..c673ac2 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -172,11 +172,15 @@ static void aarch64_cpu_finalizefn(Object *obj)
static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
- /*
- * TODO: this will need updating for system emulation,
- * when the core may be in AArch32 mode.
+ /* It's OK to look at env for the current mode here, because it's
+ * never possible for an AArch64 TB to chain to an AArch32 TB.
+ * (Otherwise we would need to use synchronize_from_tb instead.)
*/
- cpu->env.pc = value;
+ if (is_a64(&cpu->env)) {
+ cpu->env.pc = value;
+ } else {
+ cpu->env.regs[15] = value;
+ }
}
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
--
1.9.0
- Re: [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, (continued)
- [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 19/37] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 18/37] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/03/28