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Re: [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA |
Date: |
Fri, 28 Mar 2014 11:42:09 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 |
On 03/28/2014 09:09 AM, Peter Maydell wrote:
> + for (i = 0; i < maxidx; i++) {
> + hostaddr[i] = tlb_vaddr_to_host(env,
> + vaddr + TARGET_PAGE_SIZE * i,
> + 1, cpu_mmu_index(env));
> + if (!hostaddr[i]) {
> + break;
> + }
> + }
> + if (i == maxidx) {
> + /* If it's all in the TLB it's fair game for just writing to;
> + * we know we don't need to update dirty status, etc.
> + */
> + for (i = 0; i < maxidx - 1; i++) {
> + memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
> + }
> + memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
> + return;
> + }
Doesn't this fail if blocklen < TARGET_PAGE_SIZE?
Since blocklen must be a power of 4, it's either less than TARGET_PAGE_SIZE or
a multiple of TARGET_PAGE_SIZE, so that last memset looks suspect.
I think all this would be easier to follow as two cases:
if (blocklen <= TARGET_PAGE_SIZE) {
// One look up and no hostaddr array
} else {
// Multiple pages; much of what you have now, only no partial pages
}
r~
- [Qemu-devel] [PATCH v5 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, (continued)
- [Qemu-devel] [PATCH v5 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/03/28
- Re: [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/03/28