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[Qemu-devel] [RFC 5/9] acpi: add PNP0C02 to PCI0 bus
From: |
Igor Mammedov |
Subject: |
[Qemu-devel] [RFC 5/9] acpi: add PNP0C02 to PCI0 bus |
Date: |
Fri, 7 Feb 2014 13:51:32 +0100 |
Signed-off-by: Igor Mammedov <address@hidden>
---
hw/i386/acpi-build.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1dbe5ce..f0bedbd 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -492,6 +492,55 @@ static inline void acpi_add_table(GArray *table_offsets,
GArray *table_data)
g_array_append_val(table_offsets, offset);
}
+static uint8_t Hex2Digit(char c)
+{
+ if (c >= 'A') {
+ return c - 'A' + 10;
+ }
+ return c - '0';
+}
+
+static uint32_t encodeEisaId(const char *str)
+{
+ uint32_t ret;
+ g_assert(strlen(str) == 7);
+ ret = (str[0] - 0x40) << 26 |
+ (str[1] - 0x40) << 21 |
+ (str[2] - 0x40) << 16 |
+ Hex2Digit(str[3]) << 12 |
+ Hex2Digit(str[4]) << 8 |
+ Hex2Digit(str[5]) << 4 |
+ Hex2Digit(str[6]);
+ return bswap32(ret);
+}
+
+#define ACPI_SCOPE(ctx, name, ...) {\
+ GArray *name = build_alloc_array(); \
+ build_append_nameseg(name, stringify(name)); \
+ __VA_ARGS__; \
+ build_package(name, ScopeOp, 0); \
+ build_append_array(ctx, name); \
+ build_free_array(name); \
+}
+
+#define ACPI_NAME(ctx, name) { \
+ build_append_byte(ctx, NameOp); \
+ build_append_nameseg(ctx, name); \
+}
+
+#define ACPI_EISAID(ctx, val) { \
+ build_append_value(ctx, encodeEisaId(val), sizeof(uint32_t)); \
+}
+
+#define ACPI_DEVICE(ctx, name, ...) {\
+ GArray *name = build_alloc_array(); \
+ build_append_nameseg(name, stringify(name)); \
+ __VA_ARGS__; \
+ build_extop_package(name, DeviceOp); \
+ build_append_array(ctx, name); \
+ build_free_array(name); \
+}
+
/* FACS */
static void
build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
@@ -1032,6 +1081,12 @@ build_ssdt(GArray *table_data, GArray *linker,
build_pci_bus_state_cleanup(&hotplug_state);
}
+ ACPI_SCOPE(sb_scope, PCI0,
+ ACPI_DEVICE(PCI0, MRES,
+ ACPI_NAME(MRES, "_HID"); ACPI_EISAID(MRES, "PNP0C02");
+ );
+ );
+
build_package(sb_scope, op, 3);
build_append_array(table_data, sb_scope);
build_free_array(sb_scope);
--
1.7.1
- [Qemu-devel] [RFC 0/9] generate dynamic _CRS for motherboard resources, Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 1/9] Revert "pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources", Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 2/9] Revert "pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources", Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 3/9] Partial revert "pc: ACPI: expose PRST IO range via _CRS", Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 4/9] acpi: replace opencoded opcodes with defines, Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 5/9] acpi: add PNP0C02 to PCI0 bus,
Igor Mammedov <=
- [Qemu-devel] [RFC 6/9] acpi: consume GPE0 IO resources in PNP0C02 device, Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 7/9] acpi: consume CPU hotplug IO resource in PNP0C02 device, Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 8/9] pcihp: expose PCI hotplug MMIO base/length as properties of piix4pm, Igor Mammedov, 2014/02/07
- [Qemu-devel] [RFC 9/9] acpi: consume PCIHP IO resource in PNP0C02 device, Igor Mammedov, 2014/02/07
- Re: [Qemu-devel] [RFC 0/9] generate dynamic _CRS for motherboard resources, Michael S. Tsirkin, 2014/02/16