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[Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR,
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR |
Date: |
Sun, 26 Jan 2014 19:25:03 +0000 |
We have macros for marking TCGv values as unused, checking if they
are unused and comparing them to each other. However these only exist
for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well.
Signed-off-by: Peter Maydell <address@hidden>
---
tcg/tcg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c72af6c..f7efcb4 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -324,13 +324,16 @@ typedef int TCGv_i64;
#define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
#define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
+#define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
/* Dummy definition to avoid compiler warnings. */
#define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
#define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
+#define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
+#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
--
1.8.5
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, (continued)
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR,
Peter Maydell <=
- [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 16/21] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/01/26