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Re: [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit i
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc |
Date: |
Tue, 28 Jan 2014 09:34:45 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/26/2014 11:25 AM, Peter Maydell wrote:
> + do_cmop:
> + tcg_gen_setcondi_i64(tcg_invert_cond(cond), tcg_rd, tcg_rn, 0);
> + tcg_gen_subi_i64(tcg_rd, tcg_rd, 1);
> + break;
Another instance of (!test - 1) instead of -(test).
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, (continued)
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc,
Richard Henderson <=
- [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 16/21] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/01/26