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[Qemu-devel] [PULL v2 33/35] q35: gigabyte alignment for ram
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 33/35] q35: gigabyte alignment for ram |
Date: |
Sun, 26 Jan 2014 18:07:06 +0200 |
From: Gerd Hoffmann <address@hidden>
Map 2G (q35) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure this change doesn't take
away memory from 32bit guests.
Signed-off-by: Gerd Hoffmann <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/pc_q35.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 07f38ff..7104645 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -51,6 +51,7 @@
static bool has_pci_info;
static bool has_acpi_build = true;
static bool smbios_type1_defaults = true;
+static bool gigabyte_align = true;
/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
@@ -93,8 +94,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
kvmclock_create();
if (args->ram_size >= 0xb0000000) {
- above_4g_mem_size = args->ram_size - 0xb0000000;
- below_4g_mem_size = 0xb0000000;
+ ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
+ above_4g_mem_size = args->ram_size - lowmem;
+ below_4g_mem_size = lowmem;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = args->ram_size;
@@ -228,6 +230,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
static void pc_compat_1_7(QEMUMachineInitArgs *args)
{
smbios_type1_defaults = false;
+ gigabyte_align = false;
}
static void pc_compat_1_6(QEMUMachineInitArgs *args)
--
MST
- [Qemu-devel] [PULL v2 23/35] pc: set PRST base in DSDT depending on chipset, (continued)
- [Qemu-devel] [PULL v2 23/35] pc: set PRST base in DSDT depending on chipset, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 24/35] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 25/35] pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 26/35] pc: ACPI: expose PRST IO range via _CRS, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 27/35] pc: ACPI: unify source of CPU hotplug IO base/len, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 28/35] pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 29/35] acpi-test: update expected AML since recent changes, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 30/35] hw/pci: fix error flow in pci multifunction init, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 31/35] pc: Save size of RAM below 4GB, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 32/35] acpi: Fix PCI hole handling on build_srat(), Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 33/35] q35: gigabyte alignment for ram,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 34/35] q35: document gigabyte_align, Michael S. Tsirkin, 2014/01/26
- [Qemu-devel] [PULL v2 35/35] MAINTAINERS: add self as virtio co-maintainer, Michael S. Tsirkin, 2014/01/26
- Re: [Qemu-devel] [PULL v2 00/35] acpi, pci, pc, virtio fixes and enhancements, Michael S. Tsirkin, 2014/01/28
- Re: [Qemu-devel] [PULL v2 00/35] acpi, pci, pc, virtio fixes and enhancements, Peter Maydell, 2014/01/29
- Re: [Qemu-devel] [PULL v2 00/35] acpi, pci, pc, virtio fixes and enhancements, Peter Maydell, 2014/01/31