Re: [Qemu-devel] [PATCH 11/21] target-arm: Update generic cpreg code for AArch64

[Peter Maydell]

On 20 December 2013 04:24, Peter Crosthwaite
<address@hidden> wrote:
> On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell <address@hidden> wrote:
>> On 19 December 2013 06:01, Peter Crosthwaite
>> <address@hidden> wrote:
>>> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell <address@hidden> wrote:
>>>> +                    *key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>>>> +                                              r->opc0, opc1, opc2);
>>>
>>> You have mixed terminology here with "opc" and "op". Should they be
>>> unionised in ARMCPRegInfo?
>>>
>>> union {
>>>     uint8_t op1;
>>>     uint8_t opc1;
>>> };
>>
>> That seems pretty ugly to me. The terminology mixing is kind of
>> inevitable since AArch32 uses opc and AArch64 uses op.
>>
>
> The union does self-document that fact however.

I think that would be unnecessarily confusing. I'd rather just
have our code stick with the old style "opc". It's not like it's
a major difference.
> The support 32 vs 64 encoding scheme seems quite othogonal to the
> backing sotre bit width.

At the moment it isn't, though -- 64 bit registers have 64 bit
backing fields (and for AArch32 are accessed via MRRC/MCRR),
32 bit registers have 32 bit backing fields.

Bear in mind also that we have to interact with KVM, which
also treats all AArch64 sysregs as 64 bit (and AArch32
ones as 32 bit for MRC/MCR and 64 bit for MRRC/MCRR).

thanks
-- PMM