Re: [Qemu-devel] [PATCH 02/21] target-arm: A64: add support for ld/st unsigned imm

[Peter Maydell]

On 20 December 2013 16:44, Richard Henderson <address@hidden> wrote:
> On 12/20/2013 08:29 AM, Peter Maydell wrote:
>> On 20 December 2013 16:26, Richard Henderson <address@hidden> wrote:
>>> On 12/20/2013 08:08 AM, Peter Maydell wrote:
>>>>> In particular, opc = 2 && size = 2 should be unallocated.
>>>>
>>>> This is LDRSW (immediate), not unallocated, isn't it?
>>>>
>>>> I agree the decode logic isn't laid out the same as the ARM ARM,
>>>> but I'm pretty sure it's correct.
>>>
>>> Oops, typo: opc=3 && size=2.  Basically,
>>>
>>>
>>>   if opc<1> == '0' then
>>>     // store or zero-extending load
>>>     memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
>>>     regsize = if size == '11' then 64 else 32;
>>>     signed = FALSE;
>>>   else
>>>     if size == '11' then
>>>         memop = MemOp_PREFETCH;
>>>         if opc<0> == '1' then UnallocatedEncoding();
>>>     else
>>>         // sign-extending load
>>>         memop = MemOp_LOAD;
>>>         if size == '10' && opc<0> == '1' then UnallocatedEncoding();
>>>
>>> this one  ----^
>>
>> +        if (size == 3 && opc == 2) {
>> +            /* PRFM - prefetch */
>> +            return;
>> +        }
>> +        if (opc == 3 && size > 1) {
>> +            unallocated_encoding(s);
>> +            return;
>> +        }
>> +        is_store = (opc == 0);
>> +        is_signed = opc & (1<<1);
>> +        is_extended = (size < 3) && (opc & 1);
>>
>> That is caught by 'if (opc == 3 && size > 1)'.
>
> Ah, right.  In which case, patches 2, 3, 4 get
>
> Reviewed-by: Richard Henderson <address@hidden>

Thanks. I've fixed up the 1<<1 &c, so we now read

+    if (is_vector) {
+        size |= (opc & 2) << 1;
+        if (size > 4) {
+            unallocated_encoding(s);
+            return;
+        }
+        is_store = !extract32(opc, 0, 1);
+    } else {
+        if (size == 3 && opc == 2) {
+            /* PRFM - prefetch */
+            return;
+        }
+        if (opc == 3 && size > 1) {
+            unallocated_encoding(s);
+            return;
+        }
+        is_store = (opc == 0);
+        is_signed = extract32(opc, 1, 1);
+        is_extended = (size < 3) && extract32(opc, 0, 1);
+    }

Were you planning to review patches 12 ("Remove
ARMCPU/CPUARMState from cpregs APIs used by decoder")
and 19 ("Widen exclusive-access support struct fields
to 64 bits") ? I think those are the only two patches in
this set which I don't either have review comments to fix
or a reviewed-by from you now.

thanks
-- PMM