[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic |
Date: |
Tue, 10 Dec 2013 14:43:23 +0000 |
From: Peter Crosthwaite <address@hidden>
This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1 or not. i.e. it
was implementing a write-anything-to-clear strategy.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/net/cadence_gem.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 1619507..f2c734e 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1112,15 +1112,14 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
/* Squash bits which are read only in write value */
val &= ~(s->regs_ro[offset]);
- /* Preserve (only) bits which are read only in register */
- readonly = s->regs[offset];
- readonly &= s->regs_ro[offset];
-
- /* Squash bits which are write 1 to clear */
- val &= ~(s->regs_w1c[offset] & val);
+ /* Preserve (only) bits which are read only and wtc in register */
+ readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
/* Copy register write to backing store */
- s->regs[offset] = val | readonly;
+ s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
+
+ /* do w1c */
+ s->regs[offset] &= ~(s->regs_w1c[offset] & val);
/* Handle register write side effects */
switch (offset) {
--
1.8.5
- [Qemu-devel] [PULL 33/37] softfloat: Add minNum() and maxNum() functions to softfloat., (continued)
- [Qemu-devel] [PULL 33/37] softfloat: Add minNum() and maxNum() functions to softfloat., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 34/37] target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 32/37] softfloat: Remove unused argument from MINMAX macro., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 31/37] target-arm: Implement ARMv8 VSEL instruction., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 24/37] net/cadence_gem: Add missing VMSTATE_END_OF_LIST, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 10/37] target-arm: Add ARMCPU field for Linux device-tree 'compatible' string, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 28/37] net/cadence_gem: Improve can_receive debug printfery, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 29/37] net/cadence_gem: Don't rx packets when no rx buffer available, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 26/37] net/cadence_gem: Fix small packet FCS stripping, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 09/37] target-arm: Provide PSCI constants to generic QEMU code, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic,
Peter Maydell <=
- [Qemu-devel] [PULL 11/37] target-arm: Allow secondary KVM CPUs to be booted via PSCI, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 03/37] cpu/a9mpcore: reorder operations/declarations, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 22/37] net/cadence_gem: Implement SAR match bit in rx desc, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 35/37] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 19/37] net/cadence_gem: simplify rx buf descriptor walking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 15/37] hw/arm/virt: Support -cpu host, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 06/37] target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 12/37] hw/arm: Add 'virt' platform, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 30/37] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn., Peter Maydell, 2013/12/10