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[Qemu-devel] [PATCH arm-devs v1 08/13] net/cadence_gem: Implement SAR (d
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH arm-devs v1 08/13] net/cadence_gem: Implement SAR (de)activation |
Date: |
Sun, 1 Dec 2013 23:13:29 -0800 |
The Specific address registers can be enabled or disabled by software.
QEMU was assuming they where always enabled. Implement the
disable/enable feature. SARs are disabled by writing to the lower half
register. They are re-enabled by then writing the upper half.
Reported-by: Deepika Dhamija <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/net/cadence_gem.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 6f11d6a..c6eb9ab 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -382,6 +382,7 @@ typedef struct GemState {
unsigned rx_desc[2];
+ bool sar_active[4];
} GemState;
/* The broadcast MAC address: 0xFFFFFFFFFFFF */
@@ -603,7 +604,7 @@ static int gem_mac_address_filter(GemState *s, const
uint8_t *packet)
/* Check all 4 specific addresses */
gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
for (i = 3; i >= 0; i--) {
- if (!memcmp(packet, gem_spaddr + 8 * i, 6)) {
+ if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
return GEM_RX_SAR_ACCEPT + i;
}
}
@@ -985,6 +986,7 @@ static void gem_phy_reset(GemState *s)
static void gem_reset(DeviceState *d)
{
+ int i;
GemState *s = GEM(d);
DB_PRINT("\n");
@@ -1004,6 +1006,10 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF5] = 0x002f2145;
s->regs[GEM_DESCONF6] = 0x00000200;
+ for (i = 0; i < 4; ++i) {
+ s->sar_active[i] = false;
+ }
+
gem_phy_reset(s);
gem_update_int_status(s);
@@ -1153,6 +1159,18 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
s->regs[GEM_IMR] |= val;
gem_update_int_status(s);
break;
+ case GEM_SPADDR1LO:
+ case GEM_SPADDR2LO:
+ case GEM_SPADDR3LO:
+ case GEM_SPADDR4LO:
+ s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
+ break;
+ case GEM_SPADDR1HI:
+ case GEM_SPADDR2HI:
+ case GEM_SPADDR3HI:
+ case GEM_SPADDR4HI:
+ s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
+ break;
case GEM_PHYMNTNC:
if (val & GEM_PHYMNTNC_OP_W) {
uint32_t phy_addr, reg_num;
--
1.8.4.4
- Re: [Qemu-devel] [PATCH arm-devs v1 04/13] net/cadence_gem: simplify rx buf descriptor walking, (continued)
- [Qemu-devel] [PATCH arm-devs v1 05/13] net/cadence_gem: Prefetch rx descriptors ASAP, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 06/13] net/cadence_gem: Implement RX descriptor match mode flags, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 07/13] net/cadence_gem: Implement SAR match bit in rx desc, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 08/13] net/cadence_gem: Implement SAR (de)activation,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH arm-devs v1 09/13] net/cadence_gem: Fix rx multi-fragment packets, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 10/13] net/cadence_gem: Fix small packet FCS stripping, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 11/13] net/cadence_gem: Fix register w1c logic, Peter Crosthwaite, 2013/12/02
- [Qemu-devel] [PATCH arm-devs v1 12/13] net/cadence_gem: Improve can_receive debug printfery, Peter Crosthwaite, 2013/12/02