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From: | Peter Maydell |
Subject: | Re: [Qemu-devel] [PATCH arm-devs v1 07/13] net/cadence_gem: Implement SAR match bit in rx desc |
Date: | Mon, 2 Dec 2013 12:20:23 +0000 |
On 2 December 2013 07:12, Peter Crosthwaite <address@hidden> wrote: > Bit 27 of the RX buffer desc word 1 should be set when the packet was > accepted due to specific address register match. Implement. > > This feature is absent from the Xilinx documentation (UG585) but the > behaviour is tested as accurate on real hardware. > > Reported-by: Deepika Dhamija <address@hidden> > Signed-off-by: Peter Crosthwaite <address@hidden> Reviewed-by: Peter Maydell <address@hidden> -- PMM
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