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Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support
From: |
Sebastian Huber |
Subject: |
Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support |
Date: |
Mon, 16 Sep 2013 17:34:51 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130329 Thunderbird/17.0.5 |
Hello,
it would be really nice to get the CP15 VBAR support integrated. This allows
unit test suites of single address space real-time systems to catch NULL
pointer read/write access for example.
The ARM documentation says that this is a banked register that is only present
in an implementation that includes the Security Extensions. Is this equivalent
to having TrustZone?
In the ID_PFR1, Processor Feature Register 1, the bits [4:7] indicate if a
particular CPU has this feature. Is it possible to use this register to
determine the availability of the VBAR register in Qemu? This may avoid adding
a new enum arm_features.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
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- Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support,
Sebastian Huber <=