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[Qemu-devel] [PATCH v2 7/7] AARCH64: Use the spin-table method for booti
From: |
Mian M. Hamayun |
Subject: |
[Qemu-devel] [PATCH v2 7/7] AARCH64: Use the spin-table method for booting secondary processors in machvirt |
Date: |
Tue, 23 Jul 2013 11:33:16 +0200 |
From: "Mian M. Hamayun" <address@hidden>
As the SMP bootloader uses a spin-table to wait for the cpu_release_addr, we
disable the PSCI method for AArch64 in machvirt and use spin-table instead.
The CPU_RELEASE_OFFSET is introduced in machvirt and is to calculate the
cpu_release_addr by addition of this value to the memory base address, and this
value is updated in the smp bootloader using the smp_bootreg_addr board info
parameter.
Tested-by: Alexander Spyridakis <address@hidden>
Signed-off-by: Mian M. Hamayun <address@hidden>
---
hw/arm/virt.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8a2bdc7..44ab59d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -52,6 +52,7 @@
#define IO_LEN 0x000f0000
#if defined(TARGET_AARCH64)
+#define CPU_RELEASE_OFFSET 0x0000fff8
#define DEFAULT_CPU_MODEL "cortex-a57"
#elif defined(TARGET_ARM)
#define DEFAULT_CPU_MODEL "cortex-a15"
@@ -170,7 +171,7 @@ static void *initial_fdt(struct machine_info *mi)
qemu_devtree_setprop_cell(fdt, "/soc", "#interrupt-cells", 0x1);
/* No PSCI for TCG yet */
-#ifdef CONFIG_KVM
+#if defined (CONFIG_KVM) && !defined(TARGET_AARCH64)
if (kvm_enabled()) {
qemu_devtree_add_subnode(fdt, "/psci");
qemu_devtree_setprop_string(fdt, "/psci", "compatible", "arm,psci");
@@ -234,7 +235,14 @@ static void fdt_add_cpu_nodes(void *fdt, struct
machine_info *mi, int smp_cpus)
mi->cpu_compatible);
if (smp_cpus > 1) {
+#if defined(TARGET_AARCH64)
+ qemu_devtree_setprop_string(fdt, cpu_name, "enable-method",
+ "spin-table");
+ qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
+ (mi->mem_base + CPU_RELEASE_OFFSET));
+#else
qemu_devtree_setprop_string(fdt, cpu_name, "enable-method",
"psci");
+#endif
}
qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu);
@@ -437,6 +445,10 @@ static void machvirt_init(QEMUMachineInitArgs *args)
machvirt_binfo.nb_cpus = smp_cpus;
machvirt_binfo.board_id = -1;
machvirt_binfo.loader_start = mi->mem_base;
+ machvirt_binfo.smp_loader_start = mi->mem_base + 0x1000;
+#if defined(TARGET_AARCH64)
+ machvirt_binfo.smp_bootreg_addr = mi->mem_base + CPU_RELEASE_OFFSET;
+#endif
machvirt_binfo.get_dtb = machvirt_dtb;
arm_load_kernel(arm_env_get_cpu(first_cpu), &machvirt_binfo);
}
--
1.7.9.5
- [Qemu-devel] [PATCH v2 0/7] AARCH64 support on machvirt machine model using KVM, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 4/7] AARCH64: Add boot support for aarch64 processor, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 5/7] AARCH64: Disable the non-aarch64 specific reset code, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 3/7] AARCH64: Add aarch64 CPU initialization, get and put registers support, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 6/7] AARCH64: Add SMP support for aarch64 processors, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 7/7] AARCH64: Use the spin-table method for booting secondary processors in machvirt,
Mian M. Hamayun <=