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[Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair i
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions |
Date: |
Sat, 20 Apr 2013 20:56:20 +0200 |
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8298e1f..690fb45 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3293,6 +3293,52 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
/* lfs lfsu lfsux lfsx */
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
+/* lfdp */
+static void gen_lfdp(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_imm_index(ctx, EA, 0); \
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ } else {
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ }
+ tcg_temp_free(EA);
+}
+
+/* lfdpx */
+static void gen_lfdpx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ } else {
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
+ }
+ tcg_temp_free(EA);
+}
+
/* lfiwax */
static void gen_lfiwax(DisasContext *ctx)
{
@@ -9023,6 +9069,8 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
#undef GEN_STF
#undef GEN_STUF
--
1.7.10.4
- [Qemu-devel] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 09/10] target-ppc: emulate store doubleword pair instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 04/10] target-ppc: emulate cmpb instruction, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 02/10] disas: Disassemble all ppc insns for the guest, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 01/10] target-ppc: optimize fabs, fnabs, fneg, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms, Aurelien Jarno, 2013/04/20
- Re: [Qemu-devel] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Alexander Graf, 2013/04/26