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[Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction |
Date: |
Sat, 20 Apr 2013 20:56:18 +0200 |
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-ppc/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 977f9ef..4b1896f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2253,6 +2253,19 @@ static void gen_fneg(DisasContext *ctx)
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
+/* fcpsgn: PowerPC 2.05 specification */
+/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
+static void gen_fcpsgn(DisasContext *ctx)
+{
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+ cpu_fpr[rB(ctx->opcode)], 0, 63);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
/*** Floating-Point status & ctrl register ***/
/* mcrfs */
@@ -8554,6 +8567,7 @@ GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000,
PPC_FLOAT),
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
--
1.7.10.4
- [Qemu-devel] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 09/10] target-ppc: emulate store doubleword pair instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 04/10] target-ppc: emulate cmpb instruction, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 02/10] disas: Disassemble all ppc insns for the guest, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 01/10] target-ppc: optimize fabs, fnabs, fneg, Aurelien Jarno, 2013/04/20
- [Qemu-devel] [PATCH v2 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms, Aurelien Jarno, 2013/04/20
- Re: [Qemu-devel] [PATCH v2 00/10] target-ppc: emulate Power ISA 2.05 instructions, Alexander Graf, 2013/04/26