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[Qemu-devel] [PATCH 12/38] target-i386: Use add2 to implement the ADX ex
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 12/38] target-i386: Use add2 to implement the ADX extension |
Date: |
Tue, 19 Feb 2013 23:52:00 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1545e3f..3b92f3b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4169,7 +4169,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) {
goto illegal_op;
} else {
- TCGv carry_in, carry_out;
+ TCGv carry_in, carry_out, zero;
int end_op;
ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
@@ -4229,18 +4229,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
#endif
default:
/* Otherwise compute the carry-out in two steps. */
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_regs[reg]);
- tcg_gen_setcond_tl(TCG_COND_LTU, cpu_tmp4,
- cpu_T[0], cpu_regs[reg]);
- tcg_gen_add_tl(cpu_regs[reg], cpu_T[0], carry_in);
- tcg_gen_setcond_tl(TCG_COND_LTU, carry_out,
- cpu_regs[reg], cpu_T[0]);
- tcg_gen_or_tl(carry_out, carry_out, cpu_tmp4);
+ zero = tcg_const_tl(0);
+ tcg_gen_add2_tl(cpu_T[0], carry_out,
+ cpu_T[0], zero,
+ carry_in, zero);
+ tcg_gen_add2_tl(cpu_regs[reg], carry_out,
+ cpu_regs[reg], carry_out,
+ cpu_T[0], zero);
+ tcg_temp_free(zero);
break;
}
- /* We began with all flags computed to CC_SRC, and we
- have now placed the carry-out in CC_DST. All that
- is left is to record the CC_OP. */
set_cc_op(s, end_op);
}
break;
--
1.8.1.2
- [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 02/38] tcg-i386: Always implement 32-bit multiword ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 04/38] tcg: Add 64-bit multiword arithmetic operations, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 01/38] tcg: Make 32-bit multiword operations optional for 64-bit hosts, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 03/38] tcg-sparc: Always implement 32-bit multiword ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 05/38] tcg: Add signed multiword multiplication operations, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 07/38] tcg: Implement multiword multiply helpers, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 06/38] tcg: Implement a 64-bit to 32-bit extraction helper, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 08/38] tcg: Implement multiword addition helpers, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 12/38] target-i386: Use add2 to implement the ADX extension,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/38] tcg-arm: Implement muls2_i32, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 09/38] tcg-i386: Implement multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 14/38] tcg: Apply life analysis to 64-bit multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 16/38] target-s390x: Use mulu2 for mlgr insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 11/38] target-i386: Use mulu2 and muls2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 15/38] target-alpha: Use mulu2 for umulh insn, Richard Henderson, 2013/02/20