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[Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al |
Date: |
Tue, 19 Feb 2013 23:52:06 -0800 |
Cc: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/helper.c | 5 -----
target-arm/helper.h | 2 --
target-arm/translate.c | 26 ++++++++++++++------------
3 files changed, 14 insertions(+), 19 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e63da57..e97e1a5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2893,11 +2893,6 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a,
uint32_t b)
return (a & mask) | (b & ~mask);
}
-uint32_t HELPER(logicq_cc)(uint64_t val)
-{
- return (val >> 32) | (val != 0);
-}
-
/* VFP support. We follow the convention used for VFP instructions:
Single precision routines have a "s" suffix, double precision a
"d" suffix. */
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 8544f82..bca5a5b 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -46,8 +46,6 @@ DEF_HELPER_3(usat16, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-DEF_HELPER_1(logicq_cc, i32, i64)
-
DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
i32, i32, i32, i32)
DEF_HELPER_2(exception, void, env, i32)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 129f674..efe76d0 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6433,13 +6433,11 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int
rlow, int rhigh)
tcg_temp_free_i64(tmp);
}
-/* Set N and Z flags from a 64-bit value. */
-static void gen_logicq_cc(TCGv_i64 val)
+/* Set N and Z flags from hi|lo. */
+static void gen_logicq_cc(TCGv lo, TCGv hi)
{
- TCGv tmp = tcg_temp_new_i32();
- gen_helper_logicq_cc(tmp, val);
- gen_logic_CC(tmp);
- tcg_temp_free_i32(tmp);
+ tcg_gen_mov_i32(cpu_NF, hi);
+ tcg_gen_or_i32(cpu_ZF, lo, hi);
}
/* Load/Store exclusive instructions are implemented by remembering
@@ -7219,18 +7217,22 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = load_reg(s, rs);
tmp2 = load_reg(s, rm);
if (insn & (1 << 22)) {
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
+ tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
} else {
- tmp64 = gen_mulu_i64_i32(tmp, tmp2);
+ tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
}
if (insn & (1 << 21)) { /* mult accumulate */
- gen_addq(s, tmp64, rn, rd);
+ TCGv al = load_reg(s, rn);
+ TCGv ah = load_reg(s, rd);
+ tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah);
+ tcg_temp_free(al);
+ tcg_temp_free(ah);
}
if (insn & (1 << 20)) {
- gen_logicq_cc(tmp64);
+ gen_logicq_cc(tmp, tmp2);
}
- gen_storeq_reg(s, rn, rd, tmp64);
- tcg_temp_free_i64(tmp64);
+ store_reg(s, rn, tmp);
+ store_reg(s, rd, tmp2);
break;
default:
goto illegal_op;
--
1.8.1.2
- [Qemu-devel] [PATCH 08/38] tcg: Implement multiword addition helpers, (continued)
- [Qemu-devel] [PATCH 08/38] tcg: Implement multiword addition helpers, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 12/38] target-i386: Use add2 to implement the ADX extension, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 10/38] tcg-arm: Implement muls2_i32, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 09/38] tcg-i386: Implement multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 14/38] tcg: Apply life analysis to 64-bit multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 16/38] target-s390x: Use mulu2 for mlgr insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 11/38] target-i386: Use mulu2 and muls2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al,
Richard Henderson <=
- [Qemu-devel] [PATCH 15/38] target-alpha: Use mulu2 for umulh insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 28/38] target-ppc: Compute addition carry with setcond, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 32/38] target-ppc: Compute mullwo without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 34/38] target-sparc: Use mul*2 for multiply, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 33/38] target-sparc: Use official add2/sub2 interfaces for addx/subx, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 30/38] target-ppc: Implement neg in terms of subf, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 36/38] target-unicore32: Use mul*2 for do_mult, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 20/38] target-arm: Implement adc_cc inline, Richard Henderson, 2013/02/20