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[Qemu-devel] [PATCH 32/38] target-ppc: Compute mullwo without branches
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 32/38] target-ppc: Compute mullwo without branches |
Date: |
Tue, 19 Feb 2013 23:52:20 -0800 |
Cc: Alexander Graf <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 42 ++++++++++++++----------------------------
1 file changed, 14 insertions(+), 28 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4311119..f886441 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1036,35 +1036,21 @@ static void gen_mullw(DisasContext *ctx)
/* mullwo mullwo. */
static void gen_mullwo(DisasContext *ctx)
{
- int l1;
- TCGv_i64 t0, t1;
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- l1 = gen_new_label();
- /* Start with XER OV disabled, the most likely case */
- tcg_gen_movi_tl(cpu_ov, 0);
-#if defined(TARGET_PPC64)
- tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
-#else
- tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
-#endif
- tcg_gen_mul_i64(t0, t0, t1);
-#if defined(TARGET_PPC64)
- tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
-#else
- tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_gen_ext32s_i64(t1, t0);
- tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
-#endif
- tcg_gen_movi_tl(cpu_ov, 1);
- tcg_gen_movi_tl(cpu_so, 1);
- gen_set_label(l1);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_muls2_i32(t0, t1, t0, t1);
+ tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
+
+ tcg_gen_sari_i32(t0, t0, 31);
+ tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
+ tcg_gen_extu_i32_tl(cpu_ov, t0);
+ tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
}
--
1.8.1.2
- [Qemu-devel] [PATCH 09/38] tcg-i386: Implement multiword arithmetic ops, (continued)
- [Qemu-devel] [PATCH 09/38] tcg-i386: Implement multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 14/38] tcg: Apply life analysis to 64-bit multiword arithmetic ops, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 16/38] target-s390x: Use mulu2 for mlgr insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 11/38] target-i386: Use mulu2 and muls2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 15/38] target-alpha: Use mulu2 for umulh insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 28/38] target-ppc: Compute addition carry with setcond, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 32/38] target-ppc: Compute mullwo without branches,
Richard Henderson <=
- [Qemu-devel] [PATCH 34/38] target-sparc: Use mul*2 for multiply, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 33/38] target-sparc: Use official add2/sub2 interfaces for addx/subx, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 30/38] target-ppc: Implement neg in terms of subf, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 36/38] target-unicore32: Use mul*2 for do_mult, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 20/38] target-arm: Implement adc_cc inline, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 37/38] target-xtensa: Use mul*2 for mul*hi, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, Richard Henderson, 2013/02/20