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[Qemu-devel] [PATCH 027/147] target-s390: Convert LOAD AND TEST
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 027/147] target-s390: Convert LOAD AND TEST |
Date: |
Thu, 27 Sep 2012 15:40:08 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-s390x/insn-data.def | 7 +++++++
target-s390x/translate.c | 37 ++++++++++---------------------------
2 files changed, 17 insertions(+), 27 deletions(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index 796185f..7a8dcbd 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -126,6 +126,13 @@
C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0)
/* LOAD ADDRESS RELATIVE LONG */
C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0)
+/* LOAD AND TEST */
+ C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32)
+ C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64)
+ C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64)
+ C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64)
+ C(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64)
+ C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64)
/* LOAD BYTE */
C(0xb926, LBR, RRE, EI, 0, r2_8s, 0, r1_32, mov2, 0)
C(0xb906, LGBR, RRE, EI, 0, r2_8s, 0, r1, mov2, 0)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 12af61f..4ea0e95 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1349,23 +1349,6 @@ static void disas_e3(CPUS390XState *env, DisasContext*
s, int op, int r1,
op, r1, x2, b2, d2);
addr = get_address(s, x2, b2, d2);
switch (op) {
- case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
- case 0x4: /* LG r1,d2(x2,b2) */
- tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s));
- if (op == 0x2) {
- set_cc_s64(s, regs[r1]);
- }
- break;
- case 0x12: /* LT R1,D2(X2,B2) [RXY] */
- tmp2 = tcg_temp_new_i64();
- tmp32_1 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
- tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
- store_reg32(r1, tmp32_1);
- set_cc_s32(s, tmp32_1);
- tcg_temp_free_i64(tmp2);
- tcg_temp_free_i32(tmp32_1);
- break;
case 0xd: /* DSG R1,D2(X2,B2) [RXY] */
case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */
tmp2 = tcg_temp_new_i64();
@@ -3192,16 +3175,6 @@ static void disas_s390_insn(CPUS390XState *env,
DisasContext *s)
store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
- case 0x12: /* LTR R1,R2 [RR] */
- insn = ld_code2(env, s->pc);
- decode_rr(s, insn, &r1, &r2);
- tmp32_1 = load_reg32(r2);
- if (r1 != r2) {
- store_reg32(r1, tmp32_1);
- }
- set_cc_s32(s, tmp32_1);
- tcg_temp_free_i32(tmp32_1);
- break;
case 0x13: /* LCR R1,R2 [RR] */
insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
@@ -4395,6 +4368,16 @@ static void cout_nz64(DisasContext *s, DisasOps *o)
gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
}
+static void cout_s32(DisasContext *s, DisasOps *o)
+{
+ gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
+}
+
+static void cout_s64(DisasContext *s, DisasOps *o)
+{
+ gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
+}
+
static void cout_subs32(DisasContext *s, DisasOps *o)
{
gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
--
1.7.11.4
- [Qemu-devel] [PATCH 014/147] target-s390: Split o ut disas_jcc, (continued)
- [Qemu-devel] [PATCH 014/147] target-s390: Split o ut disas_jcc, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 013/147] target-s390: Add format based disassassmbly infrastructure, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 021/147] target-s390: Convert 64-bit MULTIPLY LOGICAL, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 020/147] target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 018/147] target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 019/147] target-s390: Convert MULTIPLY HALFWORD, SINGLE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 015/147] target-s390: Reorg exception handling, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 022/147] target-s390: Convert AND, OR, XOR, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 030/147] target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 031/147] target-s390: Convert STORE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 027/147] target-s390: Convert LOAD AND TEST,
Richard Henderson <=
- [Qemu-devel] [PATCH 032/147] target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 026/147] target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 033/147] target-s390: Convert BRANCH AND SAVE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 034/147] target-s390: Convert BRANCH ON CONDITION, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 028/147] target-s390: Convert LOAD LOGICAL IMMEDIATE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 035/147] target-s390: Convert BRANCH ON COUNT, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 036/147] target-s390: Convert DIVIDE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 037/147] target-s390: Send signals for divide, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 038/147] target-s390: Convert TEST UNDER MASK, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 039/147] target-s390: Convert SET ADDRESSING MODE, Richard Henderson, 2012/09/27