[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 019/147] target-s390: Convert MULTIPLY HALFWORD, SIN
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 019/147] target-s390: Convert MULTIPLY HALFWORD, SINGLE |
Date: |
Thu, 27 Sep 2012 15:40:00 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-s390x/insn-data.def | 18 +++++++
target-s390x/translate.c | 121 +++++++--------------------------------------
2 files changed, 36 insertions(+), 103 deletions(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index acde181..055113a 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -41,6 +41,24 @@
C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
+/* MULTIPLY HALFWORD */
+ C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
+ C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
+/* MULTIPLY HALFWORD IMMEDIATE */
+ C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0)
+ C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0)
+/* MULTIPLY SINGLE */
+ C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0)
+ C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0)
+ C(0xe351, MSY, RXY_a, LD, r1_o, m2_32s, new, r1_32, mul, 0)
+ C(0xb90c, MSGR, RRE, Z, r1_o, r2_o, r1, 0, mul, 0)
+ C(0xb91c, MSGFR, RRE, Z, r1_o, r2_32s, r1, 0, mul, 0)
+ C(0xe30c, MSG, RXY_a, Z, r1_o, m2_64, r1, 0, mul, 0)
+ C(0xe31c, MSGF, RXY_a, Z, r1_o, m2_32s, r1, 0, mul, 0)
+/* MULTIPLY SINGLE IMMEDIATE */
+ C(0xc201, MSFI, RIL_a, GIE, r1_o, i2, new, r1_32, mul, 0)
+ C(0xc200, MSGFI, RIL_a, GIE, r1_o, i2, r1, 0, mul, 0)
+
/* SUBTRACT */
C(0x1b00, SR, RR_a, Z, r1, r2, new, r1_32, sub, subs32)
C(0xb9f9, SRK, RRF_a, DO, r2, r3, new, r1_32, sub, subs32)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 38d8e6d..d409b93 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -575,22 +575,12 @@ static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
}
-static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32
vr)
-{
- gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
-}
-
static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
TCGv_i32 vr)
{
gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
}
-static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32
vr)
-{
- gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
-}
-
static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
@@ -1371,17 +1361,6 @@ static void disas_e3(CPUS390XState *env, DisasContext*
s, int op, int r1,
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
- case 0xc: /* MSG R1,D2(X2,B2) [RXY] */
- case 0x1c: /* MSGF R1,D2(X2,B2) [RXY] */
- tmp2 = tcg_temp_new_i64();
- if (op == 0xc) {
- tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
- } else {
- tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
- }
- tcg_gen_mul_i64(regs[r1], regs[r1], tmp2);
- tcg_temp_free_i64(tmp2);
- break;
case 0xd: /* DSG R1,D2(X2,B2) [RXY] */
case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */
tmp2 = tcg_temp_new_i64();
@@ -2337,18 +2316,6 @@ static void disas_a7(CPUS390XState *env, DisasContext
*s, int op, int r1,
store_reg(r1, tmp);
tcg_temp_free_i64(tmp);
break;
- case 0xc: /* MHI R1,I2 [RI] */
- tmp32_1 = load_reg32(r1);
- tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
- store_reg32(r1, tmp32_1);
- tcg_temp_free_i32(tmp32_1);
- break;
- case 0xd: /* MGHI R1,I2 [RI] */
- tmp = load_reg(r1);
- tcg_gen_muli_i64(tmp, tmp, i2);
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
case 0xe: /* CHI R1,I2 [RI] */
tmp32_1 = load_reg32(r1);
cmp_s32c(s, tmp32_1, i2);
@@ -2408,14 +2375,6 @@ static void disas_b2(CPUS390XState *env, DisasContext
*s, int op,
store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
- case 0x52: /* MSR R1,R2 [RRE] */
- tmp32_1 = load_reg32(r1);
- tmp32_2 = load_reg32(r2);
- tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
- store_reg32(r1, tmp32_1);
- tcg_temp_free_i32(tmp32_1);
- tcg_temp_free_i32(tmp32_2);
- break;
case 0x54: /* MVPG R1,R2 [RRE] */
tmp = load_reg(0);
tmp2 = load_reg(r1);
@@ -3083,18 +3042,6 @@ static void disas_b9(CPUS390XState *env, DisasContext
*s, int op, int r1,
store_reg(r1, tmp2);
tcg_temp_free_i64(tmp2);
break;
- case 0xc: /* MSGR R1,R2 [RRE] */
- case 0x1c: /* MSGFR R1,R2 [RRE] */
- tmp = load_reg(r1);
- tmp2 = load_reg(r2);
- if (op == 0x1c) {
- tcg_gen_ext32s_i64(tmp2, tmp2);
- }
- tcg_gen_mul_i64(tmp, tmp, tmp2);
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(tmp2);
- break;
case 0xd: /* DSGR R1,R2 [RRE] */
case 0x1d: /* DSGFR R1,R2 [RRE] */
tmp = load_reg(r1 + 1);
@@ -3820,41 +3767,6 @@ static void disas_s390_insn(CPUS390XState *env,
DisasContext *s)
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
break;
- case 0x4a: /* AH R1,D2(X2,B2) [RX] */
- case 0x4b: /* SH R1,D2(X2,B2) [RX] */
- case 0x4c: /* MH R1,D2(X2,B2) [RX] */
- insn = ld_code4(env, s->pc);
- tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
- tmp2 = tcg_temp_new_i64();
- tmp32_1 = load_reg32(r1);
- tmp32_2 = tcg_temp_new_i32();
- tmp32_3 = tcg_temp_new_i32();
-
- tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
- tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
- switch (opc) {
- case 0x4a:
- tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
- set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
- break;
- case 0x4b:
- tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
- set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
- break;
- case 0x4c:
- tcg_gen_mul_i32(tmp32_3, tmp32_1, tmp32_2);
- break;
- default:
- tcg_abort();
- }
- store_reg32(r1, tmp32_3);
-
- tcg_temp_free_i32(tmp32_1);
- tcg_temp_free_i32(tmp32_2);
- tcg_temp_free_i32(tmp32_3);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(tmp2);
- break;
case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
@@ -4022,21 +3934,6 @@ static void disas_s390_insn(CPUS390XState *env,
DisasContext *s)
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
- case 0x71: /* MS R1,D2(X2,B2) [RX] */
- insn = ld_code4(env, s->pc);
- tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
- tmp2 = tcg_temp_new_i64();
- tmp32_1 = load_reg32(r1);
- tmp32_2 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
- tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
- tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
- store_reg32(r1, tmp32_1);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(tmp2);
- tcg_temp_free_i32(tmp32_1);
- tcg_temp_free_i32(tmp32_2);
- break;
case 0x78: /* LE R1,D2(X2,B2) [RX] */
insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
@@ -4886,6 +4783,12 @@ static ExitStatus op_add(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_mul(DisasContext *s, DisasOps *o)
+{
+ tcg_gen_mul_i64(o->out, o->in1, o->in2);
+ return NO_EXIT;
+}
+
static ExitStatus op_sub(DisasContext *s, DisasOps *o)
{
tcg_gen_sub_i64(o->out, o->in1, o->in2);
@@ -4983,6 +4886,12 @@ static void in1_r1(DisasContext *s, DisasFields *f,
DisasOps *o)
o->in1 = load_reg(get_field(f, r1));
}
+static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+ o->in1 = regs[get_field(f, r1)];
+ o->g_in1 = true;
+}
+
static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
{
o->in1 = load_reg(get_field(f, r2));
@@ -5027,6 +4936,12 @@ static void in2_r2(DisasContext *s, DisasFields *f,
DisasOps *o)
o->in2 = load_reg(get_field(f, r2));
}
+static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+ o->in2 = regs[get_field(f, r2)];
+ o->g_in2 = true;
+}
+
static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
{
o->in2 = load_reg(get_field(f, r3));
--
1.7.11.4
- [Qemu-devel] [PATCH 010/147] target-s390: Fix BCR, (continued)
- [Qemu-devel] [PATCH 010/147] target-s390: Fix BCR, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 007/147] target-s390: Use TCG registers for FPR, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 014/147] target-s390: Split o ut disas_jcc, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 017/147] target-s390: Implement SUBTRACT HALFWORD, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 016/147] target-s390: Convert ADD HALFWORD, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 012/147] target-s390: Fix PSW_MASK handling, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 013/147] target-s390: Add format based disassassmbly infrastructure, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 021/147] target-s390: Convert 64-bit MULTIPLY LOGICAL, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 020/147] target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 018/147] target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 019/147] target-s390: Convert MULTIPLY HALFWORD, SINGLE,
Richard Henderson <=
- [Qemu-devel] [PATCH 015/147] target-s390: Reorg exception handling, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 022/147] target-s390: Convert AND, OR, XOR, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 023/147] target-s390: Convert COMPARE, COMPARE LOGICAL, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 025/147] target-s390: Convert LOAD ADDRESS, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 030/147] target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 031/147] target-s390: Convert STORE, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 027/147] target-s390: Convert LOAD AND TEST, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 032/147] target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 026/147] target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD, Richard Henderson, 2012/09/27
- [Qemu-devel] [PATCH 033/147] target-s390: Convert BRANCH AND SAVE, Richard Henderson, 2012/09/27