Re: [Qemu-devel] Regarding qemu support for mrrc/mcrr

[Peter Maydell]

On 4 August 2012 20:27, Aakanksha Pudipeddi <address@hidden> wrote:
> I came across this while working with qemu for a project. It looks like
> there is no support for mrrc/mcrr in qemu which results in the linux
> arch_timer code throwing a reserved instruction exception. Could you please
> let me know if anybody is working on providing this support in qemu? I'll be
> more than glad to help. Also, any suggestions on how to get started on
> implementing it would be greatly appreciated. Thanks.

This is rather vague. The important question here is "which cp15 registers
are we trying to access". I gather from your question that the answer
is "the cp15 architected timers". QEMU doesn't support those currently.
(We do now have infrastructure for adding 64 bit coprocessor registers,
so there is no extra work required for mrrc/mcrr themselves.)

We probably ought to implement the arch.timers, I agree, but it's
not on my stuff-I'm-paid-to-do TODO list at the moment. If you were to
contribute some patches that would be cool.

How to get started is a bit tricky, but definitely use head of git
master QEMU, and look at how some existing timer devices and some
existing cp15 64 bit registers are implemented, I guess. You'll need
a copy of the ARM architecture reference manual too so you know what
you're implementing.

PS: I assume you mean an UNDEF exception, there's no such thing as
a reserved instruction exception.

-- PMM