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[Qemu-devel] [PATCH 25/32] target-arm: Convert cp15 crn=0 crm={1, 2} fea
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 25/32] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers |
Date: |
Sun, 15 Apr 2012 14:46:18 +0100 |
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 14 -----------
target-arm/cpu.h | 2 -
target-arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++++++++++------
3 files changed, 54 insertions(+), 24 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0141296..f5a392b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -77,20 +77,6 @@ static void arm_cpu_reset(CPUState *s)
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
- env->cp15.c0_c1[0] = cpu->id_pfr0;
- env->cp15.c0_c1[1] = cpu->id_pfr1;
- env->cp15.c0_c1[2] = cpu->id_dfr0;
- env->cp15.c0_c1[3] = cpu->id_afr0;
- env->cp15.c0_c1[4] = cpu->id_mmfr0;
- env->cp15.c0_c1[5] = cpu->id_mmfr1;
- env->cp15.c0_c1[6] = cpu->id_mmfr2;
- env->cp15.c0_c1[7] = cpu->id_mmfr3;
- env->cp15.c0_c2[0] = cpu->id_isar0;
- env->cp15.c0_c2[1] = cpu->id_isar1;
- env->cp15.c0_c2[2] = cpu->id_isar2;
- env->cp15.c0_c2[3] = cpu->id_isar3;
- env->cp15.c0_c2[4] = cpu->id_isar4;
- env->cp15.c0_c2[5] = cpu->id_isar5;
env->cp15.c0_clid = cpu->clidr;
memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 50976d1..26bce2e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -111,8 +111,6 @@ typedef struct CPUARMState {
uint32_t c0_ccsid[16]; /* Cache size. */
uint32_t c0_clid; /* Cache level. */
uint32_t c0_cssel; /* Cache size selection. */
- uint32_t c0_c1[8]; /* Feature registers. */
- uint32_t c0_c2[8]; /* Instruction set registers. */
uint32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5048ac6..b16ab07 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -829,6 +829,60 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(env, cp_reginfo);
if (arm_feature(env, ARM_FEATURE_V6)) {
+ /* The ID registers all have impdef reset values */
+ ARMCPRegInfo v6_idregs[] = {
+ { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_pfr0 },
+ { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_pfr1 },
+ { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_dfr0 },
+ { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_afr0 },
+ { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr0 },
+ { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr1 },
+ { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr2 },
+ { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr3 },
+ { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar0 },
+ { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar1 },
+ { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar2 },
+ { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar3 },
+ { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar4 },
+ { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar5 },
+ /* 6..7 are as yet unallocated and must RAZ */
+ { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+ };
+ define_arm_cp_regs(env, v6_idregs);
define_arm_cp_regs(env, v6_cp_reginfo);
} else {
define_arm_cp_regs(env, not_v6_cp_reginfo);
@@ -2050,14 +2104,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t
insn)
default:
goto bad_reg;
}
- case 1:
- if (!arm_feature(env, ARM_FEATURE_V6))
- goto bad_reg;
- return env->cp15.c0_c1[op2];
- case 2:
- if (!arm_feature(env, ARM_FEATURE_V6))
- goto bad_reg;
- return env->cp15.c0_c2[op2];
case 3: case 4: case 5: case 6: case 7:
return 0;
default:
--
1.7.1
- [Qemu-devel] [PATCH 00/32] target-arm: refactor copro register implementation, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 06/32] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 10/32] target-arm: Convert TLS registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 01/32] target-arm: initial coprocessor register framework, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 27/32] target-arm: Convert MPIDR, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 25/32] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 26/32] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 22/32] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 19/32] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 21/32] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 17/32] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 24/32] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 20/32] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 16/32] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/04/15