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Re: [Qemu-devel] [patch V4 2/4] FreeSCALE i.MX31 support: Timers
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [patch V4 2/4] FreeSCALE i.MX31 support: Timers |
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Date: |
Thu, 15 Mar 2012 17:08:46 +0000 |
...that would work better if I cc'd the people I meant to...
On 15 March 2012 17:08, Peter Maydell <address@hidden> wrote:
> On 9 March 2012 03:27, <address@hidden> wrote:
>> Implement the timers on the FreeScale i.MX31 SoC.
>> This is not a complete implementation, but gives enough for
>> Linux to boot and run. In particular external triggers, which are
>> not useful under QEMU, are not implemented.
>
>
> CODING_STYLE wants CamelCase for typenames so 'IMXTimerGState' etc.
>
> The rest looks OK to me but I'm not very good with qemu's timer
> API. Paolo or Paul -- could you check this looks ok on that front?
>
> thanks
> -- PMM
>
>> Signed-off-by: Philip O'Sullivan <address@hidden>
>> Signed-off-by: Peter Chubb <address@hidden>
>> ---
>> Makefile.target | 2
>> hw/imx_timer.c | 575
>> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 576 insertions(+), 1 deletion(-)
>> create mode 100644 hw/imx_timer.c
>>
>> Index: qemu-working/hw/imx_timer.c
>> ===================================================================
>> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
>> +++ qemu-working/hw/imx_timer.c 2012-03-09 14:13:51.406084465 +1100
>> @@ -0,0 +1,575 @@
>> +/*
>> + * IMX31 Timer
>> + *
>> + * Copyright (c) 2008 OK Labs
>> + * Copyright (c) 2011 NICTA Pty Ltd
>> + * Originally Written by Hans Jiang
>> + * Updated by Peter Chubb
>> + *
>> + * This code is licenced under GPL version 2 or later. See
>> + * the COPYING file in the top-level directory.
>> + */
>> +
>> +#include "hw.h"
>> +#include "qemu-timer.h"
>> +#include "ptimer.h"
>> +#include "sysbus.h"
>> +
>> +//#define DEBUG_TIMER 1
>> +#ifdef DEBUG_TIMER
>> +# define DPRINTF(fmt, args...) \
>> + do { printf("imx_timer: " fmt , ##args); } while (0)
>> +#else
>> +# define DPRINTF(fmt, args...) do {} while (0)
>> +#endif
>> +
>> +/*
>> + * Define to 1 for messages about attempts to
>> + * access unimplemented registers or similar.
>> + */
>> +#define DEBUG_IMPLEMENTATION 1
>> +#if DEBUG_IMPLEMENTATION
>> +# define IPRINTF(fmt, args...) \
>> + do { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0)
>> +#else
>> +# define IPRINTF(fmt, args...) do {} while (0)
>> +#endif
>> +
>> +/*
>> + * GPT : General purpose timer
>> + *
>> + * This timer counts up continuously while it is enabled, resetting itself
>> + * to 0 after it reaches TIMER_MAX (in freerun mode) or when it
>> + * reaches the value of ocr1 (in periodic mode). Unfortunately, the
>> + * Qemu ptimer abstraction doesn't have a mode like this, so the code
>> + * uses Qemu timers directly.
>> + *
>> + * The code emulates a free-running timer by using Qemu's nanosecond
>> + * clock, suitably scaled, using the remainder after dividing by the
>> + * timer's period. In the real hardware, there are three comparison
>> + * registers that can trigger interrupts, and compare channel 1 can be
>> + * used to force-reset the timer. However, this is a `bare-bones'
>> + * implementation: only what Linux 3.0.x uses has been implemented
>> + * (free-running timer from 0 to OCR1 or TIMER_MAX) Likewise, only a
>> + * single frequency is implemented, rather than all the complicated
>> + * clock-source and prescaling logic that the real hardware implements
>> + * (most of which doesn't make sense on Qemu)
>> + */
>> +
>> +#define TIMER_MAX 0XFFFFFFFFULL
>> +#define GPT_FREQ 50000000 /* Hz == 50 MHz */
>> +
>> +/* Control register. Not all of these bits have any effect (yet) */
>> +#define GPT_CR_EN (1 << 0) /* GPT Enable */
>> +#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
>> +#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
>> +#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
>> +#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
>> +#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
>> +#define GPT_CR_CLKSRC (7 << 6) /* Clock source select (3 bits) */
>> +#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
>> +#define GPT_CR_SWR (1 << 15) /* Software Reset */
>> +#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
>> +#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
>> +#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
>> +#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
>> +#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
>> +#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
>> +#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
>> +#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
>> +
>> +#define GPT_SR_OF1 (1 << 0)
>> +#define GPT_SR_ROV (1 << 5)
>> +
>> +#define GPT_IR_OF1IE (1 << 0)
>> +#define GPT_IR_ROVIE (1 << 5)
>> +
>> +typedef struct {
>> + SysBusDevice busdev;
>> + QEMUTimer *timer;
>> + MemoryRegion iomem;
>> + uint32_t cr;
>> + uint32_t pr;
>> + uint32_t sr;
>> + uint32_t ir;
>> + uint32_t ocr1;
>> + uint32_t cnt;
>> +
>> + uint32_t waiting_rov;
>> + qemu_irq irq;
>> +} imx_timerg_state;
>> +
>> +static const VMStateDescription vmstate_imx_timerg = {
>> + .name = "imx-timerg",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(cr, imx_timerg_state),
>> + VMSTATE_UINT32(pr, imx_timerg_state),
>> + VMSTATE_UINT32(sr, imx_timerg_state),
>> + VMSTATE_UINT32(ir, imx_timerg_state),
>> + VMSTATE_UINT32(ocr1, imx_timerg_state),
>> + VMSTATE_UINT32(cnt, imx_timerg_state),
>> + VMSTATE_UINT32(waiting_rov, imx_timerg_state),
>> + VMSTATE_TIMER(timer, imx_timerg_state),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +
>> +static void imx_timerg_update(imx_timerg_state *s)
>> +{
>> + uint32_t flags = s->sr & s->ir & (GPT_SR_OF1 | GPT_SR_ROV);
>> +
>> + DPRINTF("g-timer SR: %s %s IR=%s %s, %s\n",
>> + s->sr & GPT_SR_OF1 ? "OF1" : "",
>> + s->sr & GPT_SR_ROV ? "ROV" : "",
>> + s->ir & GPT_SR_OF1 ? "OF1" : "",
>> + s->ir & GPT_SR_ROV ? "ROV" : "",
>> + s->cr & GPT_CR_EN ? "CR_EN" : "Not Enabled");
>> +
>> +
>> + qemu_set_irq(s->irq, (s->cr & GPT_CR_EN) && flags);
>> +}
>> +
>> +static uint64_t imx_timerg_update_count(imx_timerg_state *s)
>> +{
>> + uint64_t clk = qemu_get_clock_ns(vm_clock);
>> + uint64_t period = (s->cr & GPT_CR_FRR) ? TIMER_MAX + 1 : s->ocr1;
>> +
>> + s->cnt = (uint32_t)(muldiv64(clk, GPT_FREQ/1000000,
>> + 1000) % period);
>> + return clk;
>> +}
>> +
>> +static void imx_timerg_run(imx_timerg_state *s, uint32_t timeout)
>> +{
>> + uint64_t clk = imx_timerg_update_count(s);
>> + uint32_t diff_cnt;
>> +
>> + /*
>> + * For small timeouts, qemu sometimes runs too slow.
>> + * Better deliver a late interrupt than none.
>> + */
>> + if (timeout) {
>> + DPRINTF("g-run: s->cnt %u < timout %u\n", s->cnt, timeout);
>> + if (timeout > s->cnt) {
>> + diff_cnt = (timeout - s->cnt);
>> + } else {
>> + diff_cnt = timeout;
>> + }
>> + s->waiting_rov = 0;
>> + } else {
>> + DPRINTF("g-run, FRR\n");
>> + diff_cnt = (TIMER_MAX + 1) - s->cnt;
>> + s->waiting_rov = 1;
>> + }
>> + qemu_mod_timer(s->timer, clk + diff_cnt * 1000 / (GPT_FREQ/1000000));
>> +}
>> +
>> +static uint64_t imx_timerg_read(void *opaque, target_phys_addr_t offset,
>> + unsigned size)
>> +{
>> + imx_timerg_state *s = (imx_timerg_state *)opaque;
>> +
>> + DPRINTF("g-read(offset=%x)\n", offset >> 2);
>> + switch (offset >> 2) {
>> + case 0: /* Control Register */
>> + return s->cr;
>> +
>> + case 1: /* prescaler */
>> + return s->pr;
>> +
>> + case 2: /* Status Register */
>> + return s->sr;
>> +
>> + case 3: /* Interrupt Register */
>> + return s->ir;
>> +
>> + case 4: /* Output Compare Register 1 */
>> + return s->ocr1;
>> +
>> + case 9: /* cnt */
>> + imx_timerg_update_count(s);
>> + return s->cnt;
>> + }
>> +
>> + IPRINTF("imx_timerg_read: Bad offset %x\n",
>> + (int)offset >> 2);
>> + return 0;
>> +}
>> +
>> +static void imx_timerg_reset(DeviceState *dev)
>> +{
>> + imx_timerg_state *s = container_of(dev, imx_timerg_state, busdev.qdev);
>> +
>> + /*
>> + * Soft reset doesn't touch some bits; hard reset clears them
>> + */
>> + s->cr &= ~(GPT_CR_EN|GPT_CR_DOZEN|GPT_CR_WAITEN|GPT_CR_DBGEN);
>> + s->sr = 0;
>> + s->pr = 0;
>> + s->ir = 0;
>> + s->cnt = 0;
>> + s->ocr1 = TIMER_MAX;
>> + imx_timerg_update_count(s);
>> +}
>> +
>> +static void imx_timerg_write(void *opaque, target_phys_addr_t offset,
>> + uint64_t value, unsigned size)
>> +{
>> + imx_timerg_state *s = (imx_timerg_state *)opaque;
>> + DPRINTF("g-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
>> + (unsigned int)value);
>> +
>> + switch (offset >> 2) {
>> + case 0: /* CR */
>> + if (value & GPT_CR_SWR) { /* force reset */
>> + value &= ~GPT_CR_SWR;
>> + imx_timerg_reset(&s->busdev.qdev);
>> + imx_timerg_update(s);
>> + }
>> + if (!(s->cr & GPT_CR_EN) && (value & GPT_CR_EN)) {
>> + if (value & GPT_CR_ENMOD) {
>> + s->cnt = 0;
>> + }
>> + imx_timerg_run(s, s->ocr1);
>> + } else if ((s->cr & GPT_CR_EN) && !(value & GPT_CR_EN)) {
>> + qemu_del_timer(s->timer);
>> + };
>> +
>> + s->cr = value & ~0x7c;
>> + return;
>> +
>> + case 1: /* Prescaler */
>> + s->pr = value & 0xfff;
>> + return;
>> +
>> + case 2: /* SR */
>> + /*
>> + * No point in implementing the status register bits to do with
>> + * external interrupt sources.
>> + */
>> + value &= GPT_SR_OF1 | GPT_SR_ROV;
>> + s->sr &= ~value;
>> + imx_timerg_update(s);
>> + return;
>> +
>> + case 3: /* IR -- interrupt register */
>> + s->ir = value & 0x3f;
>> + imx_timerg_update(s);
>> + return;
>> +
>> + case 4: /* OCR1 -- output compare register */
>> + /* In non-freerun mode, reset count when this register is written
>> &*/
>> + s->ocr1 = value ;
>> + if (!(s->cr & GPT_CR_FRR)) {
>> + s->cnt = 0;
>> + }
>> + if (s->cr & GPT_CR_EN) {
>> + imx_timerg_run(s, s->ocr1);
>> + }
>> + return;
>> +
>> + default:
>> + IPRINTF("imx_timerg_write: Bad offset %x\n",
>> + (int)offset >> 2);
>> + }
>> +}
>> +
>> +static void imx_timerg_timeout(void *opaque)
>> +{
>> + imx_timerg_state *s = (imx_timerg_state *)opaque;
>> +
>> + DPRINTF("imx_timerg_timeout, waiting rov=%d\n", s->waiting_rov);
>> + if (s->waiting_rov) {
>> + s->sr |= GPT_SR_ROV;
>> + if (s->ocr1 == TIMER_MAX) {
>> + s->sr |= GPT_SR_OF1;
>> + }
>> + imx_timerg_run(s, s->ocr1);
>> + } else {
>> + s->sr |= GPT_SR_OF1;
>> + imx_timerg_run(s, 0);
>> + }
>> + imx_timerg_update(s);
>> +}
>> +
>> +static const MemoryRegionOps imx_timerg_ops = {
>> + .read = imx_timerg_read,
>> + .write = imx_timerg_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +
>> +static int imx_timerg_init(SysBusDevice *dev)
>> +{
>> + imx_timerg_state *s = FROM_SYSBUS(imx_timerg_state, dev);
>> +
>> + sysbus_init_irq(dev, &s->irq);
>> + memory_region_init_io(&s->iomem, &imx_timerg_ops,
>> + s, "imxg-timer",
>> + 0x00001000);
>> + sysbus_init_mmio(dev, &s->iomem);
>> +
>> + s->timer = qemu_new_timer_ns(vm_clock, imx_timerg_timeout, s);
>> + /* Hard reset resets extra bits in CR */
>> + s->cr = 0;
>> + return 0;
>> +}
>> +
>> +
>> +
>> +/*
>> + * EPIT: Enhanced periodic interrupt timer
>> + */
>> +
>> +#define TIMER_TICK_LENGTH 5000
>> +
>> +#define CR_EN (1 << 0)
>> +#define CR_ENMOD (1 << 1)
>> +#define CR_OCIEN (1 << 2)
>> +#define CR_RLD (1 << 3)
>> +#define CR_PRESCALE_SHIFT (4)
>> +#define CR_PRESCALE_MASK (0xfff << CR_PRESCALE_SHIFT)
>> +#define CR_SWR (1 << 16)
>> +#define CR_IOVW (1 << 17)
>> +#define CR_DBGEN (1 << 18)
>> +#define CR_EPIT (1 << 19)
>> +#define CR_DOZEN (1 << 20)
>> +#define CR_STOPEN (1 << 21)
>> +#define CR_CLKSRC_SHIFT (24)
>> +#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
>> +
>> +/*
>> + * Exact clock frequencies vary from board to board.
>> + * These are typical.
>> + */
>> +static const uint32_t clocks[] = {
>> + 0, /* disabled */
>> + 53200000, /* ipg_clk, ~50MHz */
>> + 53200000, /* ipg_clk_highfreq */
>> + 32768, /* ipg_clk_32k -- ~32kHz */
>> +};
>> +
>> +
>> +typedef struct {
>> + SysBusDevice busdev;
>> + ptimer_state *timer;
>> + MemoryRegion iomem;
>> + uint32_t cr;
>> + uint32_t lr;
>> + uint32_t cmp;
>> +
>> + uint32_t freq;
>> + int int_level;
>> + qemu_irq irq;
>> +} imx_timerp_state;
>> +
>> +/*
>> + * Update interrupt status
>> + */
>> +static void imx_timerp_update(imx_timerp_state *s)
>> +{
>> + if (s->int_level && (s->cr & CR_OCIEN)) {
>> + qemu_irq_raise(s->irq);
>> + } else {
>> + qemu_irq_lower(s->irq);
>> + }
>> +}
>> +
>> +static void imx_timerp_reset(DeviceState *dev)
>> +{
>> + imx_timerp_state *s = container_of(dev, imx_timerp_state, busdev.qdev);
>> +
>> + s->cr = 0;
>> + s->lr = 0xffffffff;
>> + s->int_level = 0;
>> + s->cmp = 0;
>> + ptimer_stop(s->timer);
>> + ptimer_set_count(s->timer, 0xffffffff);
>> +}
>> +
>> +static uint64_t imx_timerp_read(void *opaque, target_phys_addr_t offset,
>> + unsigned size)
>> +{
>> + imx_timerp_state *s = (imx_timerp_state *)opaque;
>> +
>> + DPRINTF("p-read(offset=%x)\n", offset);
>> + switch (offset >> 2) {
>> + case 0: /* Control Register */
>> + return s->cr;
>> +
>> + case 1: /* Status Register */
>> + return s->int_level;
>> +
>> + case 2: /* LR - ticks*/
>> + return s->lr;
>> +
>> + case 3: /* CMP */
>> + return s->cmp;
>> +
>> + case 4: /* CNT */
>> + return ptimer_get_count(s->timer);
>> + }
>> + IPRINTF("imx_timerp_read: Bad offset %x\n",
>> + (int)offset >> 2);
>> + return 0;
>> +}
>> +
>> +static void set_timerp_freq(imx_timerp_state *s)
>> +{
>> + int clksrc;
>> + unsigned prescaler;
>> + uint32_t freq;
>> +
>> + clksrc = (s->cr & CR_CLKSRC_MASK) >> CR_CLKSRC_SHIFT;
>> + prescaler = 1 + ((s->cr & CR_PRESCALE_MASK) >> CR_PRESCALE_SHIFT);
>> + DPRINTF("ptimer clksrc %d, prescaler %d", clksrc, prescaler);
>> + freq = clocks[clksrc] / prescaler;
>> +
>> + DPRINTF("Setting ptimer to frequency %d\n", freq);
>> + s->freq = freq;
>> +
>> + if (freq) {
>> + ptimer_set_freq(s->timer, freq);
>> + }
>> +}
>> +
>> +static void imx_timerp_write(void *opaque, target_phys_addr_t offset,
>> + uint64_t value, unsigned size)
>> +{
>> + imx_timerp_state *s = (imx_timerp_state *)opaque;
>> + DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
>> + (unsigned int)value);
>> +
>> + switch (offset >> 2) {
>> + case 0: /* CR */
>> + if (value & CR_SWR) {
>> + imx_timerp_reset(&s->busdev.qdev);
>> + value &= ~CR_SWR;
>> + }
>> + s->cr = value & 0x03ffffff;
>> + set_timerp_freq(s);
>> +
>> + if (s->freq && (s->cr & CR_EN)) {
>> + ptimer_run(s->timer, 0);
>> + } else {
>> + ptimer_stop(s->timer);
>> + }
>> + break;
>> +
>> + case 1: /* SR - ACK*/
>> + s->int_level = 0;
>> + imx_timerp_update(s);
>> + break;
>> +
>> + case 2: /* LR - set ticks */
>> + s->lr = value;
>> + ptimer_set_limit(s->timer, value, !!(s->cr & CR_IOVW));
>> + break;
>> +
>> + case 3: /* CMP */
>> + s->cmp = value;
>> + break;
>> +
>> + default:
>> + IPRINTF("imx_timerp_write: Bad offset %x\n",
>> + (int)offset >> 2);
>> + }
>> +}
>> +
>> +static void imx_timerp_tick(void *opaque)
>> +{
>> + imx_timerp_state *s = (imx_timerp_state *)opaque;
>> +
>> + s->int_level = 1;
>> + if (!(s->cr & CR_RLD)) {
>> + ptimer_set_count(s->timer, 0xffffffff);
>> + }
>> + imx_timerp_update(s);
>> +}
>> +
>> +static const MemoryRegionOps imx_timerp_ops = {
>> + .read = imx_timerp_read,
>> + .write = imx_timerp_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static const VMStateDescription vmstate_imx_timerp = {
>> + .name = "imx-timerp",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(cr, imx_timerp_state),
>> + VMSTATE_UINT32(lr, imx_timerp_state),
>> + VMSTATE_UINT32(cmp, imx_timerp_state),
>> + VMSTATE_UINT32(freq, imx_timerp_state),
>> + VMSTATE_INT32(int_level, imx_timerp_state),
>> + VMSTATE_PTIMER(timer, imx_timerp_state),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static int imx_timerp_init(SysBusDevice *dev)
>> +{
>> + imx_timerp_state *s = FROM_SYSBUS(imx_timerp_state, dev);
>> + QEMUBH *bh;
>> +
>> + DPRINTF("imx_timerp_init\n");
>> +
>> + sysbus_init_irq(dev, &s->irq);
>> + memory_region_init_io(&s->iomem, &imx_timerp_ops,
>> + s, "imxp-timer",
>> + 0x00001000);
>> + sysbus_init_mmio(dev, &s->iomem);
>> +
>> + bh = qemu_bh_new(imx_timerp_tick, s);
>> + s->timer = ptimer_init(bh);
>> +
>> + return 0;
>> +}
>> +
>> +static void imx_timerg_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
>> + k->init = imx_timerg_init;
>> + dc->vmsd = &vmstate_imx_timerg;
>> + dc->reset = imx_timerg_reset;
>> + dc->desc = "i.MX general timer";
>> +}
>> +
>> +static void imx_timerp_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
>> + k->init = imx_timerp_init;
>> + dc->vmsd = &vmstate_imx_timerp;
>> + dc->reset = imx_timerp_reset;
>> + dc->desc = "i.MX periodic timer";
>> +}
>> +
>> +static TypeInfo imx_timerp_info = {
>> + .name = "imx_timerp",
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(imx_timerp_state),
>> + .class_init = imx_timerp_class_init,
>> +};
>> +
>> +static TypeInfo imx_timerg_info = {
>> + .name = "imx_timerg",
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(imx_timerg_state),
>> + .class_init = imx_timerg_class_init,
>> +};
>> +
>> +static void imx_timer_register_types(void)
>> +{
>> + type_register_static(&imx_timerp_info);
>> + type_register_static(&imx_timerg_info);
>> +}
>> +
>> +type_init(imx_timer_register_types)
>> Index: qemu-working/Makefile.target
>> ===================================================================
>> --- qemu-working.orig/Makefile.target 2012-03-09 14:13:50.038065728 +1100
>> +++ qemu-working/Makefile.target 2012-03-09 14:13:51.406084465 +1100
>> @@ -379,7 +379,7 @@ obj-arm-y += vexpress.o
>> obj-arm-y += strongarm.o
>> obj-arm-y += collie.o
>> obj-arm-y += pl041.o lm4549.o
>> -obj-arm-y += imx_serial.o
>> +obj-arm-y += imx_serial.o imx_timer.o
>> obj-arm-$(CONFIG_FDT) += device_tree.o
>>
>> obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
>>
>
>
>
> --
> 12345678901234567890123456789012345678901234567890123456789012345678901234567890
> 1 2 3 4 5 6 7
> 8
--
12345678901234567890123456789012345678901234567890123456789012345678901234567890
1 2 3 4 5 6 7 8