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Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts c
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable |
Date: |
Wed, 11 Jan 2012 16:40:14 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:9.0) Gecko/20111220 Thunderbird/9.0 |
Am 11.01.2012 16:26, schrieb Mark Langsdorf:
> Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,
> and create a configurable property for each defaulting to 96 and 64
> (respectively) so that device modelers can set the value appropriately
> for their SoC. Other ARM processors also set their maximum number of
> used IRQs appropriately.
>
> Set the maximum theoretically number of GIC interrupts to 1020 and
> update the save/restore code to only use the appropriate number for
> each SoC.
>
> Signed-off-by: Mark Langsdorf <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Andreas
> ---
> Changes from v7
> Removed unnecessary vmstate_register
> Changes from v6
> Removed trailing whitespace
> armv7m_nvic uses num_irq properly
> Some comments changed
> Changes from v5
> Clarify the commit message
> Rename GIC_NIRQ to GIC_MAXIRQ and change usage slightly
> Makes num-irq to uint32_t in all cases
> Clarify the error message
> Clarify documentation on the num-irq qdev property use in all files
> Changes from v4
> None
> Changes from v3
> Increase maximum number of GIC interrupts to 1020
> Remove SoC/implementation specific GIC_NIRQ #defs
> Added properties code to arm11mp
> Changed error handling for too many interrupts
> Redid save/load handling
> Changes from v2
> Skipped
> Changes from v1
> Increase the number of a9mp interrupts to 192
> Add a property defaulting to 96
> Add a num_irq member in the gic state structure
> Use the num_irq value as appropriate
> Add num_irq argument to gic_init()
> Add num_irq to various CPU calls to gic_init
--
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GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
- [Qemu-devel] [PATCH v8 0/6] arm: add support for Calxeda Highbank SoC, (continued)
- [Qemu-devel] [PATCH v8 0/6] arm: add support for Calxeda Highbank SoC, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Peter Maydell, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH v8 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/11
- [Qemu-devel] [PATCH v8 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable,
Andreas Färber <=
- Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable, Peter Maydell, 2012/01/11
[Qemu-devel] [PATCH v9 0/6] arm: add support for Calxeda Highbank SoC, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mitsyanko Igor, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Andreas Färber, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mitsyanko Igor, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/12