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[Qemu-devel] [PATCH 39/64] pseries: More complete WIMG validation in H_E
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 39/64] pseries: More complete WIMG validation in H_ENTER code |
Date: |
Thu, 6 Oct 2011 10:05:41 +0200 |
From: David Gibson <address@hidden>
Currently our implementation of the H_ENTER hypercall, which inserts a
mapping in the hash page table assumes that only ordinary memory is ever
mapped, and only permits mapping attribute bits accordingly (WIMG==0010).
However, we intend to start adding emulated IO to the pseries platform
(and real IO with PCI passthrough on kvm) which means this simple test
will no longer suffice.
This patch extends the h_enter validation code to check if the given
address is a RAM address. If it is it enforces WIMG==0010, otherwise
it assumes that it is an IO mapping and instead enforces WIMG=010x.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/spapr.c | 3 ++-
hw/spapr.h | 1 +
hw/spapr_hcall.c | 22 ++++++++++++++++++----
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 9eefef9..00aed62 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -336,7 +336,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
}
/* allocate RAM */
- ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
+ spapr->ram_limit = ram_size;
+ ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit);
cpu_register_physical_memory(0, ram_size, ram_offset);
/* allocate hash page table. For now we always make this 16mb,
diff --git a/hw/spapr.h b/hw/spapr.h
index 009c459..3d21b7a 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -10,6 +10,7 @@ typedef struct sPAPREnvironment {
struct VIOsPAPRBus *vio_bus;
struct icp_state *icp;
+ target_phys_addr_t ram_limit;
void *htab;
long htab_size;
target_phys_addr_t fdt_addr, rtas_addr;
diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index f7ead04..70f853c 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -99,6 +99,8 @@ static target_ulong h_enter(CPUState *env, sPAPREnvironment
*spapr,
target_ulong pte_index = args[1];
target_ulong pteh = args[2];
target_ulong ptel = args[3];
+ target_ulong page_shift = 12;
+ target_ulong raddr;
target_ulong i;
uint8_t *hpte;
@@ -111,6 +113,7 @@ static target_ulong h_enter(CPUState *env, sPAPREnvironment
*spapr,
#endif
if ((ptel & 0xff000) == 0) {
/* 16M page */
+ page_shift = 24;
/* lowest AVA bit must be 0 for 16M pages */
if (pteh & 0x80) {
return H_PARAMETER;
@@ -120,12 +123,23 @@ static target_ulong h_enter(CPUState *env,
sPAPREnvironment *spapr,
}
}
- /* FIXME: bounds check the pa? */
+ raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
- /* Check WIMG */
- if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
- return H_PARAMETER;
+ if (raddr < spapr->ram_limit) {
+ /* Regular RAM - should have WIMG=0010 */
+ if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
+ return H_PARAMETER;
+ }
+ } else {
+ /* Looks like an IO address */
+ /* FIXME: What WIMG combinations could be sensible for IO?
+ * For now we allow WIMG=010x, but are there others? */
+ /* FIXME: Should we check against registered IO addresses? */
+ if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
+ return H_PARAMETER;
+ }
}
+
pteh &= ~0x60ULL;
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
--
1.6.0.2
- [Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs, (continued)
- [Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 52/64] openpic: Unfold read_IRQreg, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 14/64] device tree: add nop_node, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 47/64] Implement POWER7's CFAR in TCG, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 42/64] pseries: use macro for firmware filename, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 57/64] KVM: Update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 46/64] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 53/64] openpic: Unfold write_IRQreg, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 54/64] ppc: move ADB stuff from ppc_mac.h to adb.h, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 26/64] device tree: add add_subnode command, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 39/64] pseries: More complete WIMG validation in H_ENTER code,
Alexander Graf <=
- Re: [Qemu-devel] [PULL 00/64] ppc patch queue 2011-10-06, Blue Swirl, 2011/10/08