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[Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs |
Date: |
Thu, 6 Oct 2011 10:05:13 +0200 |
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in
the code exporting the numbers out and fix an integer overflow while at it.
Signed-off-by: Alexander Graf <address@hidden>
---
v1 -> v2:
- Max cpus is 15 due to cINT routing
- Report nb_cpus not MAX_CPUS in MPIC capabilities
---
hw/openpic.c | 10 +++-------
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 109c1bc..03e442b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -63,7 +63,7 @@
#elif defined(USE_MPCxxx)
-#define MAX_CPU 2
+#define MAX_CPU 15
#define MAX_IRQ 128
#define MAX_DBL 0
#define MAX_MBX 0
@@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
break;
case IRQ_IDE:
tmp = val & 0xC0000000;
- tmp |= val & ((1 << MAX_CPU) - 1);
+ tmp |= val & ((1ULL << MAX_CPU) - 1);
opp->src[n_IRQ].ide = tmp;
DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
break;
@@ -1283,7 +1283,7 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x80000000;
/* Initialise controller registers */
- mpp->frep = 0x004f0002;
+ mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
mpp->veni = VENI;
mpp->pint = 0x00000000;
mpp->spve = 0x0000FFFF;
@@ -1684,10 +1684,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int
nb_cpus,
{mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
};
- /* XXX: for now, only one CPU is supported */
- if (nb_cpus != 1)
- return NULL;
-
mpp = g_malloc0(sizeof(openpic_t));
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
--
1.6.0.2
- [Qemu-devel] [PATCH 41/64] pseries: Add real mode debugging hcalls, (continued)
- [Qemu-devel] [PATCH 41/64] pseries: Add real mode debugging hcalls, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 62/64] pseries: Refactor spapr irq allocation, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 49/64] vscsi: send the CHECK_CONDITION status down together with autosense data, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 43/64] KVM: Update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 50/64] Gdbstub: handle read of fpscr, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 55/64] PPC: Fix via-cuda memory registration, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 27/64] device tree: dont fail operations, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 56/64] PPC: Fix heathrow PIC to use little endian MMIO, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 44/64] kvm: ppc: booke206: use MMU API, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 19/64] PPC: bamboo: Use kvm api for freq and clock frequencies, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs,
Alexander Graf <=
- [Qemu-devel] [PATCH 52/64] openpic: Unfold read_IRQreg, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 14/64] device tree: add nop_node, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 47/64] Implement POWER7's CFAR in TCG, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 42/64] pseries: use macro for firmware filename, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 57/64] KVM: Update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 46/64] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 53/64] openpic: Unfold write_IRQreg, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 54/64] ppc: move ADB stuff from ppc_mac.h to adb.h, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 26/64] device tree: add add_subnode command, Alexander Graf, 2011/10/06
- [Qemu-devel] [PATCH 39/64] pseries: More complete WIMG validation in H_ENTER code, Alexander Graf, 2011/10/06