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[Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN()
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN() |
Date: |
Wed, 17 Aug 2011 15:47:15 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
fpu/softfloat-specialize.h | 20 ++++++++++++++++++++
target-m68k/helper.c | 13 ++++++++++++-
2 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index c165205..e051549 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -387,6 +387,26 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
return 1;
}
}
+#elif defined(TARGET_M68K)
+static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
+ flag aIsLargerSignificand)
+{
+ /* If either operand, but not both operands, of an operation is a
+ * nonsignaling NAN, then that NAN is returned as the result. If both
+ * operands are nonsignaling NANs, then the destination operand
+ * nonsignaling NAN is returned as the result.
+ */
+
+ if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (bIsQNaN) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
#else
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f67bfba..14a6ae6 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -244,6 +244,8 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char
*name)
void cpu_reset(CPUM68KState *env)
{
+ int i;
+
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
log_cpu_state(env, 0);
@@ -254,7 +256,16 @@ void cpu_reset(CPUM68KState *env)
env->sr = 0x2700;
#endif
m68k_switch_sp(env);
- /* ??? FP regs should be initialized to NaN. */
+
+ for (i = 0; i < 8; i++) {
+ env->fregs[i].l.upper = floatx80_default_nan_high;
+ env->fregs[i].l.lower = 0xffffffffffffffffULL;
+ }
+ env->fp0h = floatx80_default_nan_high;
+ env->fp0l = 0xffffffffffffffffULL;
+ env->fp1h = floatx80_default_nan_high;
+ env->fp1l = 0xffffffffffffffffULL;
+
env->cc_op = CC_OP_FLAGS;
/* TODO: We should set PC from the interrupt vector. */
env->pc = 0;
--
1.7.2.3
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", (continued)
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(),
Bryce Lanham <=
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 068/111] m68k: correct addsubq, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl, Bryce Lanham, 2011/08/17